Add iCE40 gfx for span-4 wires between IO tiles

Signed-off-by: Clifford Wolf <clifford@clifford.at>

5 files changed, 126 insertions, 7 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 91dc5d66..68af1ac7 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -226,9 +226,12 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
     return PORT_INOUT;
 }
 
-std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId) const
+std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
+
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", bel.index)));
+
     return ret;
 }
 
@@ -342,7 +345,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
     std::vector<std::pair<IdString, std::string>> ret;
     auto &wi = chip_info->wire_data[wire.index];
 
-    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wi.netidx)));
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wire.index)));
 
     ret.push_back(std::make_pair(id("GRID_X"), stringf("%d", wi.x)));
     ret.push_back(std::make_pair(id("GRID_Y"), stringf("%d", wi.y)));
@@ -402,9 +405,12 @@ IdString Arch::getPipName(PipId pip) const
 
 IdString Arch::getPipType(PipId pip) const { return IdString(); }
 
-std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId) const
+std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
+
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", pip.index)));
+
     return ret;
 }
 
diff --git a/ice40/arch.h b/ice40/arch.h
index 871b25fb..37f663d9 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -108,8 +108,6 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     };
 
     RelPtr<char> name;
-    int32_t netidx;
-
     int32_t num_uphill, num_downhill;
     RelPtr<int32_t> pips_uphill, pips_downhill;
 
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index a28cba4a..c33d736c 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -1265,8 +1265,6 @@ for t in range(num_tile_types):
 bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
 for wire, info in enumerate(wireinfo):
     bba.s(info["name"], "name")
-    bba.u32(wire, "netidx")
-
     bba.u32(info["num_uphill"], "num_uphill")
     bba.u32(info["num_downhill"], "num_downhill")
     bba.r(info["list_uphill"], "pips_uphill")
diff --git a/ice40/gfx.cc b/ice40/gfx.cc
index 79350ad0..d6fcf5df 100644
--- a/ice40/gfx.cc
+++ b/ice40/gfx.cc
@@ -411,6 +411,64 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id,
         g.push_back(el);
     }
 
+    // Horizontal IO Span-4 Wires
+
+    if (id >= TILE_WIRE_SPAN4_HORZ_R_0 && id <= TILE_WIRE_SPAN4_HORZ_L_15) {
+        int idx = id - TILE_WIRE_SPAN4_HORZ_R_0;
+
+        float y1 = y + 1.0 - (0.03 + 0.0025 * (60 - idx));
+        float y2 = y + 1.0 - (0.03 + 0.0025 * (60 - idx - 4));
+
+        el.x1 = x;
+        el.x2 = x + 0.9;
+        el.y1 = y1;
+        el.y2 = y1;
+        g.push_back(el);
+
+        if (idx <= 15) {
+            el.x1 = x + 0.9;
+            el.x2 = x + 1.0;
+            el.y1 = y1;
+            el.y2 = y2;
+            g.push_back(el);
+        }
+
+        el.x1 = x + main_swbox_x1 + 0.0025 * (idx + 35);
+        el.x2 = el.x1;
+        el.y1 = y1;
+        el.y2 = y + main_swbox_y2;
+        g.push_back(el);
+    }
+
+    // Vertical IO Span-4 Wires
+
+    if (id >= TILE_WIRE_SPAN4_VERT_B_0 && id <= TILE_WIRE_SPAN4_VERT_T_15) {
+        int idx = id - TILE_WIRE_SPAN4_VERT_B_0;
+
+        float x1 = x + 0.03 + 0.0025 * (60 - idx);
+        float x2 = x + 0.03 + 0.0025 * (60 - idx - 4);
+
+        el.y1 = y + 1.00;
+        el.y2 = y + 0.10;
+        el.x1 = x1;
+        el.x2 = x1;
+        g.push_back(el);
+
+        if (idx <= 15) {
+            el.y1 = y + 0.10;
+            el.y2 = y;
+            el.x1 = x1;
+            el.x2 = x2;
+            g.push_back(el);
+        }
+
+        el.y1 = y + 1.0 - (0.03 + 0.0025 * (270 - idx));
+        el.y2 = el.y1;
+        el.x1 = x1;
+        el.x2 = x + main_swbox_x1;
+        g.push_back(el);
+    }
+
     // Global2Local
 
     if (id >= TILE_WIRE_GLB2LOCAL_0 && id <= TILE_WIRE_GLB2LOCAL_3) {
@@ -711,6 +769,21 @@ static bool getWireXY_main(GfxTileWireId id, float &x, float &y)
         return true;
     }
 
+    // IO Span-4 Wires
+
+    if (id >= TILE_WIRE_SPAN4_HORZ_R_0 && id <= TILE_WIRE_SPAN4_HORZ_L_15) {
+        int idx = id - TILE_WIRE_SPAN4_HORZ_R_0;
+        y = main_swbox_y2;
+        x = main_swbox_x1 + 0.0025 * (idx + 35);
+        return true;
+    }
+
+    if (id >= TILE_WIRE_SPAN4_VERT_B_0 && id <= TILE_WIRE_SPAN4_VERT_T_15) {
+        int idx = id - TILE_WIRE_SPAN4_VERT_B_0;
+        y = 1.0 - (0.03 + 0.0025 * (270 - idx));
+        x = main_swbox_x1;
+    }
+
     // Global2Local
 
     if (id >= TILE_WIRE_GLB2LOCAL_0 && id <= TILE_WIRE_GLB2LOCAL_3) {
diff --git a/ice40/gfx.h b/ice40/gfx.h
index 5401a410..94c2538e 100644
--- a/ice40/gfx.h
+++ b/ice40/gfx.h
@@ -664,6 +664,50 @@ enum GfxTileWireId
     TILE_WIRE_SPAN12_HORZ_22,
     TILE_WIRE_SPAN12_HORZ_23,
 
+    TILE_WIRE_SPAN4_VERT_B_0,
+    TILE_WIRE_SPAN4_VERT_B_1,
+    TILE_WIRE_SPAN4_VERT_B_2,
+    TILE_WIRE_SPAN4_VERT_B_3,
+    TILE_WIRE_SPAN4_VERT_B_4,
+    TILE_WIRE_SPAN4_VERT_B_5,
+    TILE_WIRE_SPAN4_VERT_B_6,
+    TILE_WIRE_SPAN4_VERT_B_7,
+    TILE_WIRE_SPAN4_VERT_B_8,
+    TILE_WIRE_SPAN4_VERT_B_9,
+    TILE_WIRE_SPAN4_VERT_B_10,
+    TILE_WIRE_SPAN4_VERT_B_11,
+    TILE_WIRE_SPAN4_VERT_B_12,
+    TILE_WIRE_SPAN4_VERT_B_13,
+    TILE_WIRE_SPAN4_VERT_B_14,
+    TILE_WIRE_SPAN4_VERT_B_15,
+
+    TILE_WIRE_SPAN4_VERT_T_12,
+    TILE_WIRE_SPAN4_VERT_T_13,
+    TILE_WIRE_SPAN4_VERT_T_14,
+    TILE_WIRE_SPAN4_VERT_T_15,
+
+    TILE_WIRE_SPAN4_HORZ_R_0,
+    TILE_WIRE_SPAN4_HORZ_R_1,
+    TILE_WIRE_SPAN4_HORZ_R_2,
+    TILE_WIRE_SPAN4_HORZ_R_3,
+    TILE_WIRE_SPAN4_HORZ_R_4,
+    TILE_WIRE_SPAN4_HORZ_R_5,
+    TILE_WIRE_SPAN4_HORZ_R_6,
+    TILE_WIRE_SPAN4_HORZ_R_7,
+    TILE_WIRE_SPAN4_HORZ_R_8,
+    TILE_WIRE_SPAN4_HORZ_R_9,
+    TILE_WIRE_SPAN4_HORZ_R_10,
+    TILE_WIRE_SPAN4_HORZ_R_11,
+    TILE_WIRE_SPAN4_HORZ_R_12,
+    TILE_WIRE_SPAN4_HORZ_R_13,
+    TILE_WIRE_SPAN4_HORZ_R_14,
+    TILE_WIRE_SPAN4_HORZ_R_15,
+
+    TILE_WIRE_SPAN4_HORZ_L_12,
+    TILE_WIRE_SPAN4_HORZ_L_13,
+    TILE_WIRE_SPAN4_HORZ_L_14,
+    TILE_WIRE_SPAN4_HORZ_L_15,
+
     TILE_WIRE_PLLIN,
     TILE_WIRE_PLLOUT_A,
     TILE_WIRE_PLLOUT_B