aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorgatecat <gatecat@ds0.me>2021-03-10 10:03:24 +0000
committerGitHub <noreply@github.com>2021-03-10 10:03:24 +0000
commit7f0c23dff356a43e29205598afaa9aff672a8e0e (patch)
tree4d0da6dd965b2445efe8c5f8d6b9701baff8b9ac
parentd1f44fe91ad29b45c715918c97fba4bb243c631f (diff)
parent979e7b8709c77e30a6b01345e6541cbb7c03e7a8 (diff)
downloadnextpnr-7f0c23dff356a43e29205598afaa9aff672a8e0e.tar.gz
nextpnr-7f0c23dff356a43e29205598afaa9aff672a8e0e.tar.bz2
nextpnr-7f0c23dff356a43e29205598afaa9aff672a8e0e.zip
Merge pull request #617 from YosysHQ/no-absl-on-wasi
Only depend on Abseil in threaded builds.
-rw-r--r--CMakeLists.txt6
-rw-r--r--common/router2.cc6
2 files changed, 10 insertions, 2 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 2c8e38a8..b3df6a58 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -274,8 +274,10 @@ foreach (family ${ARCH})
# Include the family-specific CMakeFile
include(${family}/family.cmake)
foreach (target ${family_targets})
- target_link_libraries(${target} PRIVATE absl::flat_hash_map)
- target_link_libraries(${target} PRIVATE absl::flat_hash_set)
+ if (USE_THREADS)
+ target_link_libraries(${target} PRIVATE absl::flat_hash_map)
+ target_link_libraries(${target} PRIVATE absl::flat_hash_set)
+ endif()
# Include family-specific source files to all family targets and set defines appropriately
target_include_directories(${target} PRIVATE ${family}/ ${CMAKE_CURRENT_BINARY_DIR}/generated/)
diff --git a/common/router2.cc b/common/router2.cc
index 0a3a4e94..b145db81 100644
--- a/common/router2.cc
+++ b/common/router2.cc
@@ -27,7 +27,9 @@
*/
#include "router2.h"
+#if !defined(NPNR_DISABLE_THREADS)
#include <absl/container/flat_hash_map.h>
+#endif
#include <algorithm>
#include <boost/container/flat_map.hpp>
#include <chrono>
@@ -191,7 +193,11 @@ struct Router2
}
}
+#if defined(NPNR_DISABLE_THREADS)
+ std::unordered_map<WireId, int> wire_to_idx;
+#else
absl::flat_hash_map<WireId, int> wire_to_idx;
+#endif
std::vector<PerWireData> flat_wires;
PerWireData &wire_data(WireId w) { return flat_wires[wire_to_idx.at(w)]; }