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| author | gatecat <gatecat@ds0.me> | 2021-05-14 22:44:06 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 14:54:33 +0100 |
| commit | 8bc9732d49fe645f29bc840c503ddb94a07f6e4c (patch) | |
| tree | 8108cf795c62ed1421d18ec5a07e8229d0c26140 | |
| parent | 757a10c247615e85b6a04cb9524536857e54ced6 (diff) | |
| download | nextpnr-8bc9732d49fe645f29bc840c503ddb94a07f6e4c.tar.gz nextpnr-8bc9732d49fe645f29bc840c503ddb94a07f6e4c.tar.bz2 nextpnr-8bc9732d49fe645f29bc840c503ddb94a07f6e4c.zip | |
mistral: PKREG bits appear to be mirrored within a half?
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | mistral/bitstream.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 6921bbb5..8e78b228 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -246,8 +246,9 @@ struct MistralBitgen cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, alm, true); // Flipflop configuration const std::array<CycloneV::bmux_type_t, 2> ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL}; - const std::array<CycloneV::bmux_type_t, 4> pkreg{CycloneV::TPKREG0, CycloneV::TPKREG1, CycloneV::BPKREG0, - CycloneV::BPKREG1}; + // This isn't a typo; the *PKREG* bits really are mirrored. + const std::array<CycloneV::bmux_type_t, 4> pkreg{CycloneV::TPKREG1, CycloneV::TPKREG0, CycloneV::BPKREG1, + CycloneV::BPKREG0}; const std::array<CycloneV::bmux_type_t, 2> clk_sel{CycloneV::TCLK_SEL, CycloneV::BCLK_SEL}, clr_sel{CycloneV::TCLR_SEL, CycloneV::BCLR_SEL}, sclr_dis{CycloneV::TSCLR_DIS, CycloneV::BSCLR_DIS}, |