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author | Maciej Dudek <mdudek@antmicro.com> | 2022-05-27 10:58:24 +0200 |
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committer | Maciej Dudek <mdudek@antmicro.com> | 2022-05-27 10:58:39 +0200 |
commit | 8c4e3e91ccd7fc5c994f05e67a4605290d72079e (patch) | |
tree | ee828f02b95cf7bb962c9d2b69a6cef3d74cb6ff | |
parent | 4ecbf6c6e941699413e0d0bba660fc9dc18efcfe (diff) | |
download | nextpnr-8c4e3e91ccd7fc5c994f05e67a4605290d72079e.tar.gz nextpnr-8c4e3e91ccd7fc5c994f05e67a4605290d72079e.tar.bz2 nextpnr-8c4e3e91ccd7fc5c994f05e67a4605290d72079e.zip |
Change write_dcc to work with tilegroups from prjoxide
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
-rw-r--r-- | nexus/fasm.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/nexus/fasm.cc b/nexus/fasm.cc index 3ed5785e..de03fb82 100644 --- a/nexus/fasm.cc +++ b/nexus/fasm.cc @@ -533,11 +533,10 @@ struct NexusFasmWriter void write_dcc(const CellInfo *cell) { BelId bel = cell->bel; - push_tile(bel.tile); - push_belname(bel); + push_bel(bel); write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer write_cell_muxes(cell); - pop(2); + pop(); } // Write config for DCS void write_dcs(const CellInfo *cell) |