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| author | gatecat <gatecat@ds0.me> | 2021-05-15 10:26:27 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 14:54:33 +0100 |
| commit | 9221acc9e211766d79d7c7dde5d5fc8bb053354d (patch) | |
| tree | 406159fd26ce543165b729cb441c486195d707d6 | |
| parent | 4d32c4f2fcb5c5e5ca21100f4473acb2c4cda3b0 (diff) | |
| download | nextpnr-9221acc9e211766d79d7c7dde5d5fc8bb053354d.tar.gz nextpnr-9221acc9e211766d79d7c7dde5d5fc8bb053354d.tar.bz2 nextpnr-9221acc9e211766d79d7c7dde5d5fc8bb053354d.zip | |
mistral: Fix ENA and ACLR bitstream generation
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | mistral/arch.h | 1 | ||||
| -rw-r--r-- | mistral/bitstream.cc | 4 | ||||
| -rw-r--r-- | mistral/globals.cc | 4 | ||||
| -rw-r--r-- | mistral/lab.cc | 6 |
4 files changed, 11 insertions, 4 deletions
diff --git a/mistral/arch.h b/mistral/arch.h index 97d6a2b1..2360fb20 100644 --- a/mistral/arch.h +++ b/mistral/arch.h @@ -65,6 +65,7 @@ struct LABInfo std::array<WireId, 2> aclr_wires; WireId sclr_wire, sload_wire; // TODO: LAB configuration (control set etc) + std::array<bool, 2> aclr_used; }; struct PinInfo diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 2c7f7862..e31b94af 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -283,7 +283,7 @@ struct MistralBitgen if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to // ensure different constants don't collide cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, true); - cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, !ff->ffInfo.ctrlset.ena.inverted); + cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, ff->ffInfo.ctrlset.ena.inverted); } else { cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, false); } @@ -315,7 +315,7 @@ struct MistralBitgen const std::array<CycloneV::bmux_type_t, 2> aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL}; for (int i = 0; i < 2; i++) { // Quartus seems to set unused ACLRs to CLKI2... - if (ctx->getBoundWireNet(lab_data.aclr_wires[i]) == nullptr) + if (!lab_data.aclr_used[i]) cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, CycloneV::CLKI2); else cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1); diff --git a/mistral/globals.cc b/mistral/globals.cc index 97e35518..9cbabbca 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -26,8 +26,8 @@ NEXTPNR_NAMESPACE_BEGIN void Arch::create_clkbuf(int x, int y) { for (int z = 0; z < 4; z++) { - if (z != 2) - continue; // TODO: why do other Zs not work? + if (z != 2) + continue; // TODO: why do other Zs not work? // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); diff --git a/mistral/lab.cc b/mistral/lab.cc index 838c72a3..d34cc0ca 100644 --- a/mistral/lab.cc +++ b/mistral/lab.cc @@ -616,6 +616,11 @@ void Arch::assign_control_sets(uint32_t lab) bool legal = worker.run(this, lab); NPNR_ASSERT(legal); auto &lab_data = labs.at(lab); + + for (int j = 0; j < 2; j++) { + lab_data.aclr_used[j] = false; + } + for (uint8_t alm = 0; alm < 10; alm++) { auto &alm_data = lab_data.alms.at(alm); for (uint8_t i = 0; i < 4; i++) { @@ -648,6 +653,7 @@ void Arch::assign_control_sets(uint32_t lab) log_info("Assigned ACLR set %d to FF %s (%s)\n", i, nameOf(ff), getCtx()->nameOfBel(ff_bel)); } reserve_route(lab_data.aclr_wires[j], aclr_wire); + lab_data.aclr_used[j] = (aclr_sig.net != nullptr); alm_data.aclr_idx[i / 2] = j; break; } |