machxo2: Remove generic API functions from Arch.

2 files changed, 0 insertions, 262 deletions

diff --git a/machxo2/arch.cc b/machxo2/arch.cc
index 6979673a..56899ced 100644
--- a/machxo2/arch.cc
+++ b/machxo2/arch.cc
@@ -28,236 +28,6 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-WireInfo &Arch::wire_info(IdString wire)
-{
-    auto w = wires.find(wire);
-    if (w == wires.end())
-        NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(this));
-    return w->second;
-}
-
-PipInfo &Arch::pip_info(IdString pip)
-{
-    auto p = pips.find(pip);
-    if (p == pips.end())
-        NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(this));
-    return p->second;
-}
-
-BelInfo &Arch::bel_info(IdString bel)
-{
-    auto b = bels.find(bel);
-    if (b == bels.end())
-        NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(this));
-    return b->second;
-}
-
-void Arch::addWire(IdString name, IdString type, int x, int y)
-{
-    NPNR_ASSERT(wires.count(name) == 0);
-    WireInfo &wi = wires[name];
-    wi.name = name;
-    wi.type = type;
-    wi.x = x;
-    wi.y = y;
-
-    wire_ids.push_back(name);
-}
-
-void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc)
-{
-    NPNR_ASSERT(pips.count(name) == 0);
-    PipInfo &pi = pips[name];
-    pi.name = name;
-    pi.type = type;
-    pi.srcWire = srcWire;
-    pi.dstWire = dstWire;
-    pi.delay = delay;
-    pi.loc = loc;
-
-    wire_info(srcWire).downhill.push_back(name);
-    wire_info(dstWire).uphill.push_back(name);
-    pip_ids.push_back(name);
-
-    if (int(tilePipDimZ.size()) <= loc.x)
-        tilePipDimZ.resize(loc.x + 1);
-
-    if (int(tilePipDimZ[loc.x].size()) <= loc.y)
-        tilePipDimZ[loc.x].resize(loc.y + 1);
-
-    gridDimX = std::max(gridDimX, loc.x + 1);
-    gridDimY = std::max(gridDimY, loc.x + 1);
-    tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
-}
-
-void Arch::addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay)
-{
-    NPNR_ASSERT(pips.count(name) == 0);
-    PipInfo &pi = pips[name];
-    pi.name = name;
-    pi.type = type;
-    pi.srcWire = srcWire;
-    pi.dstWire = dstWire;
-    pi.delay = delay;
-
-    wire_info(srcWire).aliases.push_back(name);
-    pip_ids.push_back(name);
-}
-
-void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
-{
-    NPNR_ASSERT(bels.count(name) == 0);
-    NPNR_ASSERT(bel_by_loc.count(loc) == 0);
-    BelInfo &bi = bels[name];
-    bi.name = name;
-    bi.type = type;
-    bi.x = loc.x;
-    bi.y = loc.y;
-    bi.z = loc.z;
-    bi.gb = gb;
-
-    bel_ids.push_back(name);
-    bel_by_loc[loc] = name;
-
-    if (int(bels_by_tile.size()) <= loc.x)
-        bels_by_tile.resize(loc.x + 1);
-
-    if (int(bels_by_tile[loc.x].size()) <= loc.y)
-        bels_by_tile[loc.x].resize(loc.y + 1);
-
-    bels_by_tile[loc.x][loc.y].push_back(name);
-
-    if (int(tileBelDimZ.size()) <= loc.x)
-        tileBelDimZ.resize(loc.x + 1);
-
-    if (int(tileBelDimZ[loc.x].size()) <= loc.y)
-        tileBelDimZ[loc.x].resize(loc.y + 1);
-
-    gridDimX = std::max(gridDimX, loc.x + 1);
-    gridDimY = std::max(gridDimY, loc.x + 1);
-    tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
-}
-
-void Arch::addBelInput(IdString bel, IdString name, IdString wire)
-{
-    NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
-    PinInfo &pi = bel_info(bel).pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_IN;
-
-    wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
-    wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
-
-void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
-{
-    NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
-    PinInfo &pi = bel_info(bel).pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_OUT;
-
-    wire_info(wire).uphill_bel_pin = BelPin{bel, name};
-    wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
-
-void Arch::addBelInout(IdString bel, IdString name, IdString wire)
-{
-    NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
-    PinInfo &pi = bel_info(bel).pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_INOUT;
-
-    wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
-    wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
-
-void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); }
-
-void Arch::addGroupWire(IdString group, IdString wire) { groups[group].wires.push_back(wire); }
-
-void Arch::addGroupPip(IdString group, IdString pip) { groups[group].pips.push_back(pip); }
-
-void Arch::addGroupGroup(IdString group, IdString grp) { groups[group].groups.push_back(grp); }
-
-void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
-{
-    decal_graphics[decal].push_back(graphic);
-    refreshUi();
-}
-
-void Arch::setWireDecal(WireId wire, DecalXY decalxy)
-{
-    wire_info(wire).decalxy = decalxy;
-    refreshUiWire(wire);
-}
-
-void Arch::setPipDecal(PipId pip, DecalXY decalxy)
-{
-    pip_info(pip).decalxy = decalxy;
-    refreshUiPip(pip);
-}
-
-void Arch::setBelDecal(BelId bel, DecalXY decalxy)
-{
-    bel_info(bel).decalxy = decalxy;
-    refreshUiBel(bel);
-}
-
-void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
-{
-    groups[group].decalxy = decalxy;
-    refreshUiGroup(group);
-}
-
-void Arch::setWireAttr(IdString wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
-
-void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
-
-void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
-
-void Arch::setLutK(int K) { args.K = K; }
-
-void Arch::setDelayScaling(double scale, double offset)
-{
-    args.delayScale = scale;
-    args.delayOffset = offset;
-}
-
-void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
-
-void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay)
-{
-    if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE)
-        cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT;
-    if (get_or_default(cellTiming[cell].portClasses, toPort, TMG_IGNORE) == TMG_IGNORE)
-        cellTiming[cell].portClasses[toPort] = TMG_COMB_OUTPUT;
-    cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay;
-}
-
-void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
-{
-    TimingClockingInfo ci;
-    ci.clock_port = clock;
-    ci.edge = RISING_EDGE;
-    ci.setup = setup;
-    ci.hold = hold;
-    cellTiming[cell].clockingInfo[port].push_back(ci);
-    cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT;
-}
-
-void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq)
-{
-    TimingClockingInfo ci;
-    ci.clock_port = clock;
-    ci.edge = RISING_EDGE;
-    ci.clockToQ = clktoq;
-    cellTiming[cell].clockingInfo[port].push_back(ci);
-    cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
-}
-
 // ---------------------------------------------------------------
 
 Arch::Arch(ArchArgs args) : chipName("generic"), args(args)
diff --git a/machxo2/arch.h b/machxo2/arch.h
index cbfb943d..ba34f8dc 100644
--- a/machxo2/arch.h
+++ b/machxo2/arch.h
@@ -140,38 +140,6 @@ struct Arch : BaseCtx
 
     std::unordered_map<IdString, CellTiming> cellTiming;
 
-    void addWire(IdString name, IdString type, int x, int y);
-    void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
-    void addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay);
-
-    void addBel(IdString name, IdString type, Loc loc, bool gb);
-    void addBelInput(IdString bel, IdString name, IdString wire);
-    void addBelOutput(IdString bel, IdString name, IdString wire);
-    void addBelInout(IdString bel, IdString name, IdString wire);
-
-    void addGroupBel(IdString group, IdString bel);
-    void addGroupWire(IdString group, IdString wire);
-    void addGroupPip(IdString group, IdString pip);
-    void addGroupGroup(IdString group, IdString grp);
-
-    void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
-    void setWireDecal(WireId wire, DecalXY decalxy);
-    void setPipDecal(PipId pip, DecalXY decalxy);
-    void setBelDecal(BelId bel, DecalXY decalxy);
-    void setGroupDecal(GroupId group, DecalXY decalxy);
-
-    void setWireAttr(IdString wire, IdString key, const std::string &value);
-    void setPipAttr(IdString pip, IdString key, const std::string &value);
-    void setBelAttr(IdString bel, IdString key, const std::string &value);
-
-    void setLutK(int K);
-    void setDelayScaling(double scale, double offset);
-
-    void addCellTimingClock(IdString cell, IdString port);
-    void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
-    void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
-    void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
-
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.