Add counter test.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

5 files changed, 71 insertions, 0 deletions

diff --git a/fpga_interchange/examples/counter/Makefile b/fpga_interchange/examples/counter/Makefile
new file mode 100644
index 00000000..27d20cdf
--- /dev/null
+++ b/fpga_interchange/examples/counter/Makefile
@@ -0,0 +1,8 @@
+DESIGN := counter
+DESIGN_TOP := top
+PACKAGE := cpg236
+
+include ../template.mk
+
+build/counter.json: counter.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/counter/counter.v b/fpga_interchange/examples/counter/counter.v
new file mode 100644
index 00000000..00f52a20
--- /dev/null
+++ b/fpga_interchange/examples/counter/counter.v
@@ -0,0 +1,15 @@
+module top(input clk, input rst, output [7:4] io_led);
+
+reg [31:0] counter = 32'b0;
+
+assign io_led = counter >> 22;
+
+always @(posedge clk)
+begin
+    if(rst)
+        counter <= 32'b0;
+    else
+        counter <= counter + 1;
+end
+
+endmodule
diff --git a/fpga_interchange/examples/counter/counter.xdc b/fpga_interchange/examples/counter/counter.xdc
new file mode 100644
index 00000000..7cbe67f6
--- /dev/null
+++ b/fpga_interchange/examples/counter/counter.xdc
@@ -0,0 +1,22 @@
+## basys3 breakout board
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property PACKAGE_PIN V17 [get_ports rst]
+#set_property PACKAGE_PIN U16 [get_ports io_led[0]]
+#set_property PACKAGE_PIN E19 [get_ports io_led[1]]
+#set_property PACKAGE_PIN U19 [get_ports io_led[2]]
+#set_property PACKAGE_PIN V19 [get_ports io_led[3]]
+set_property PACKAGE_PIN U16 [get_ports io_led[4]]
+set_property PACKAGE_PIN E19 [get_ports io_led[5]]
+set_property PACKAGE_PIN U19 [get_ports io_led[6]]
+set_property PACKAGE_PIN V19 [get_ports io_led[7]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports rst]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
+#set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]]
+#set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]]
+#set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]]
+#set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]]
diff --git a/fpga_interchange/examples/counter/run.tcl b/fpga_interchange/examples/counter/run.tcl
new file mode 100644
index 00000000..245aab04
--- /dev/null
+++ b/fpga_interchange/examples/counter/run.tcl
@@ -0,0 +1,15 @@
+yosys -import
+
+read_verilog counter.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+techmap -map ../remap.v
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/counter.json
diff --git a/fpga_interchange/examples/remap.v b/fpga_interchange/examples/remap.v
new file mode 100644
index 00000000..6dfc0b4a
--- /dev/null
+++ b/fpga_interchange/examples/remap.v
@@ -0,0 +1,11 @@
+module INV(input I, output O);
+
+LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
+
+endmodule
+
+module BUF(input I, output O);
+
+LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
+
+endmodule