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authorDavid Shah <davey1576@gmail.com>2018-07-12 10:09:56 +0200
committerDavid Shah <davey1576@gmail.com>2018-07-12 10:09:56 +0200
commit9e06954edb1071b4ef2e7ebc525d8c6de42d0fc3 (patch)
tree4132ddeaed634bd041ebc500d46cb7f70493bf59
parentb58d665b43dae745b6aee4c56106a45f48379220 (diff)
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ecp5: Improving SLICE bel
Signed-off-by: David Shah <davey1576@gmail.com>
-rw-r--r--ecp5/portpins.inc18
-rw-r--r--ecp5/synth/cells.v12
-rwxr-xr-xecp5/trellis_import.py29
3 files changed, 58 insertions, 1 deletions
diff --git a/ecp5/portpins.inc b/ecp5/portpins.inc
index cfe0a349..ab0ebe9f 100644
--- a/ecp5/portpins.inc
+++ b/ecp5/portpins.inc
@@ -14,6 +14,16 @@ X(FXB)
X(CLK)
X(LSR)
X(CE)
+X(DI0)
+X(DI1)
+X(WD0)
+X(WD1)
+X(WAD0)
+X(WAD1)
+X(WAD2)
+X(WAD3)
+X(WRE)
+X(WCK)
X(F0)
X(Q0)
X(F1)
@@ -21,6 +31,14 @@ X(Q1)
X(FCO)
X(OFX0)
X(OFX1)
+X(WDO0)
+X(WDO1)
+X(WDO2)
+X(WDO3)
+X(WADO0)
+X(WADO1)
+X(WADO2)
+X(WADO3)
X(I)
X(O)
diff --git a/ecp5/synth/cells.v b/ecp5/synth/cells.v
index d2c6d560..353b8ada 100644
--- a/ecp5/synth/cells.v
+++ b/ecp5/synth/cells.v
@@ -4,10 +4,20 @@ module TRELLIS_SLICE(
input A1, B1, C1, D1,
input M0, M1,
input FCI, FXA, FXB,
+
input CLK, LSR, CE,
+ input DI0, DI1,
+
+ input WD0, WD1,
+ input WAD0, WAD1, WAD2, WAD3,
+ input WRE, WCK,
+
output F0, Q0,
output F1, Q1,
- output FCO, OFX0, OFX1
+ output FCO, OFX0, OFX1,
+
+ output WDO0, WDO1, WDO2, WDO3,
+ output WADO0, WADO1, WADO2, WADO3
);
parameter MODE = "LOGIC";
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 5fdd7296..5eca057a 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -124,14 +124,43 @@ def add_slice(x, y, z):
add_bel_input(x, y, idx, "LSR", x, y, "LSR{}_SLICE".format(z))
add_bel_input(x, y, idx, "CE", x, y, "CE{}_SLICE".format(z))
+ add_bel_input(x, y, idx, "DI0", x, y, "DI{}_SLICE".format(lc0))
+ add_bel_input(x, y, idx, "DI1", x, y, "DI{}_SLICE".format(lc1))
+
+ if z == 0 or z == 1:
+ add_bel_input(x, y, idx, "WD0", x, y, "WD0{}_SLICE".format(l))
+ add_bel_input(x, y, idx, "WD1", x, y, "WD1{}_SLICE".format(l))
+
+ add_bel_input(x, y, idx, "WAD0", x, y, "WAD0{}_SLICE".format(l))
+ add_bel_input(x, y, idx, "WAD1", x, y, "WAD1{}_SLICE".format(l))
+ add_bel_input(x, y, idx, "WAD2", x, y, "WAD2{}_SLICE".format(l))
+ add_bel_input(x, y, idx, "WAD3", x, y, "WAD3{}_SLICE".format(l))
+
+ add_bel_input(x, y, idx, "WRE", x, y, "WRE{}_SLICE".format(z))
+ add_bel_input(x, y, idx, "WCK", x, y, "WCK{}_SLICE".format(z))
+
add_bel_output(x, y, idx, "F0", x, y, "F{}_SLICE".format(lc0))
add_bel_output(x, y, idx, "Q0", x, y, "Q{}_SLICE".format(lc0))
add_bel_output(x, y, idx, "F1", x, y, "F{}_SLICE".format(lc1))
add_bel_output(x, y, idx, "Q1", x, y, "Q{}_SLICE".format(lc1))
+ add_bel_output(x, y, idx, "OFX0", x, y, "F5{}_SLICE".format(l))
+ add_bel_output(x, y, idx, "OFX1", x, y, "FX{}_SLICE".format(l))
+
add_bel_output(x, y, idx, "FCO", x, y, "FCO{}_SLICE".format(l if z < 3 else ""))
+ if z == 2:
+ add_bel_output(x, y, idx, "WDO0", x, y, "WDO0C_SLICE")
+ add_bel_output(x, y, idx, "WDO1", x, y, "WDO1C_SLICE")
+ add_bel_output(x, y, idx, "WDO2", x, y, "WDO2C_SLICE")
+ add_bel_output(x, y, idx, "WDO3", x, y, "WDO3C_SLICE")
+
+ add_bel_output(x, y, idx, "WADO0", x, y, "WADO0C_SLICE")
+ add_bel_output(x, y, idx, "WADO1", x, y, "WADO1C_SLICE")
+ add_bel_output(x, y, idx, "WADO2", x, y, "WADO2C_SLICE")
+ add_bel_output(x, y, idx, "WADO3", x, y, "WADO3C_SLICE")
+
def add_pio(x, y, z):
idx = len(loc_bels[x, y])