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authorSylvain Munaut <tnt@246tNt.com>2018-11-16 22:55:31 +0100
committerSylvain Munaut <tnt@246tNt.com>2018-11-19 18:20:20 +0100
commitac5d767d4fc96a02cfcf5f06930c1aa5f41c97b4 (patch)
treed8efda8bf0cce2c863d73e00cc363c5d9ed1e99a
parent5fb3353557853178c2787ea8a80afddf5ace8a4d (diff)
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ice40/pack: Stop looking for BEL when we have one during PLL placement
Ideally we should first process all the PLL that are constrained somehow (either explicitely or because they are PAD) and then free place the rest. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
-rw-r--r--ice40/pack.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/ice40/pack.cc b/ice40/pack.cc
index c7614830..c91c97be 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -881,6 +881,7 @@ static void pack_special(Context *ctx)
packed->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
pll_bel = bel;
constrained = true;
+ break;
}
if (!constrained) {
log_error("Could not constrain PLL '%s' to any PLL Bel (too many PLLs?)\n",