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| author | gatecat <gatecat@ds0.me> | 2023-03-20 09:10:02 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-03-20 18:54:57 +0100 |
| commit | b3c33bd0ab3cd123aa73e9cb46dea41baadf6dd5 (patch) | |
| tree | 5994bb4c52cc36cb28e50280c47fa472fff24ff9 | |
| parent | d7e450b7b61ccb35515956c4d68f708a39552e49 (diff) | |
| download | nextpnr-b3c33bd0ab3cd123aa73e9cb46dea41baadf6dd5.tar.gz nextpnr-b3c33bd0ab3cd123aa73e9cb46dea41baadf6dd5.tar.bz2 nextpnr-b3c33bd0ab3cd123aa73e9cb46dea41baadf6dd5.zip | |
ice40: Fix BRAM NegClk bitstream logic
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | ice40/bitstream.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 72343d75..533f310a 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -636,12 +636,12 @@ void write_asc(const Context *ctx, std::ostream &out) bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W); int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE); int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE); - if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) { - set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r); - set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w); - } else { + if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + } else { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w); } set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); |