diff options
| author | Sylvain Munaut <tnt@246tNt.com> | 2020-03-29 10:27:42 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-03-29 10:27:42 +0200 |
| commit | bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57 (patch) | |
| tree | 6c77696798a669a784d37e2a41def9d98b3c3822 | |
| parent | a3ede0293a50c910e7d96319b2084d50f2501a6b (diff) | |
| download | nextpnr-bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57.tar.gz nextpnr-bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57.tar.bz2 nextpnr-bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57.zip | |
ice40: Fix output register timing analysis for registered output enable
Wrong bits were being tested. [5:4] is what's controlling the output
enable path.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| -rw-r--r-- | ice40/arch.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index a43c4c21..6d07a949 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -1037,7 +1037,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } } if (port == id_OUTPUT_ENABLE) { - if ((cell->ioInfo.pintype & 0x18) == 0x18) { + if ((cell->ioInfo.pintype & 0x30) == 0x30) { return TMG_REGISTER_INPUT; } else { return TMG_ENDPOINT; |