[interchange] Scale edge cost of pseudo pips.

Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

2 files changed, 12 insertions, 5 deletions

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 5b38a879..f9209922 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -1959,6 +1959,17 @@ void Arch::explain_bel_status(BelId bel) const
     site.explain(getCtx());
 }
 
+DelayQuad Arch::getPipDelay(PipId pip) const {
+    // FIXME: Implement when adding timing-driven place and route.
+    const auto & pip_data = pip_info(chip_info, pip);
+
+    // Scale pseudo-pips by the number of wires they consume to make them
+    // more expensive than a single edge.  This approximation exists soley to
+    // make the non-timing driven solution avoid thinking that pseudo-pips
+    // are the same cost as regular pips.
+    return DelayQuad(100*(1+pip_data.pseudo_cell_wires.size()));
+}
+
 // Instance constraint templates.
 template void Arch::ArchConstraints::bindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
 template void Arch::ArchConstraints::unbindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange);
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 0b1cfa43..a6ea70d8 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -622,11 +622,7 @@ struct Arch : ArchAPI<ArchRanges>
         return canonical_wire(chip_info, pip.tile, loc_info(chip_info, pip).pip_data[pip.index].dst_index);
     }
 
-    DelayQuad getPipDelay(PipId pip) const final
-    {
-        // FIXME: Implement when adding timing-driven place and route.
-        return DelayQuad(100);
-    }
+    DelayQuad getPipDelay(PipId pip) const final;
 
     DownhillPipRange getPipsDownhill(WireId wire) const final
     {