aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDavid Shah <davey1576@gmail.com>2018-07-23 10:32:42 +0200
committerDavid Shah <davey1576@gmail.com>2018-07-23 10:32:42 +0200
commitd0ed23d673013b4fc44f5e938bc74103d1268c13 (patch)
tree3f7e638f8157267a485592e1a82a383785f5ce05
parent3788bd26e609f8488ba0f135731a46fb32afa843 (diff)
downloadnextpnr-d0ed23d673013b4fc44f5e938bc74103d1268c13.tar.gz
nextpnr-d0ed23d673013b4fc44f5e938bc74103d1268c13.tar.bz2
nextpnr-d0ed23d673013b4fc44f5e938bc74103d1268c13.zip
ecp5: Remove obsolete db entries, add Bel z-position
Signed-off-by: David Shah <davey1576@gmail.com>
-rw-r--r--ecp5/arch.h5
-rwxr-xr-xecp5/trellis_import.py16
2 files changed, 2 insertions, 19 deletions
diff --git a/ecp5/arch.h b/ecp5/arch.h
index cce9f09d..9d99da8c 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -56,6 +56,7 @@ NPNR_PACKED_STRUCT(struct BelWirePOD {
NPNR_PACKED_STRUCT(struct BelInfoPOD {
RelPtr<char> name;
BelType type;
+ int32_t z;
int32_t num_bel_wires;
RelPtr<BelWirePOD> bel_wires;
});
@@ -85,10 +86,6 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
int32_t num_uphill, num_downhill;
RelPtr<PipLocatorPOD> pips_uphill, pips_downhill;
- int32_t num_bels_downhill;
- BelPortPOD bel_uphill;
- RelPtr<BelPortPOD> bels_downhill;
-
int32_t num_bel_pins;
RelPtr<BelPortPOD> bel_pins;
});
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index b0cbdd90..b5cd53f1 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -401,12 +401,6 @@ def write_database(dev_name, ddrg, endianness):
for up in wire.arcsUphill:
write_loc(up.rel, "rel_loc")
bba.u32(up.id, "index")
- if len(wire.belsDownhill) > 0:
- bba.l("loc%d_wire%d_downbels" % (idx, wire_idx), "BelPortPOD")
- for db in wire.belsDownhill:
- write_loc(db.bel.rel, "rel_bel_loc")
- bba.u32(db.bel.id, "bel_index")
- bba.u32(portpins[ddrg.to_str(db.pin)], "port")
if len(wire.belPins) > 0:
bba.l("loc%d_wire%d_belpins" % (idx, wire_idx), "BelPortPOD")
for bp in wire.belPins:
@@ -421,15 +415,6 @@ def write_database(dev_name, ddrg, endianness):
bba.u32(len(wire.arcsDownhill), "num_downhill")
bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
- bba.u32(len(wire.belsDownhill), "num_bels_downhill")
- write_loc(wire.belUphill.bel.rel, "uphill_bel_loc")
- if wire.belUphill.pin != -1:
- bba.u32(wire.belUphill.bel.id, "uphill_bel_idx")
- bba.u32(portpins[ddrg.to_str(wire.belUphill.pin)], "uphill_bel_pin")
- else:
- bba.u32(0xFFFFFFFF, "bel_uphill.bel_index")
- bba.u32(0, "bel_uphill.port")
- bba.r("loc%d_wire%d_downbels" % (idx, wire_idx) if len(wire.belsDownhill) > 0 else None, "bels_downhill")
bba.u32(len(wire.belPins), "num_bel_pins")
bba.r("loc%d_wire%d_belpins" % (idx, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
@@ -447,6 +432,7 @@ def write_database(dev_name, ddrg, endianness):
bel = loctype.bels[bel_idx]
bba.s(ddrg.to_str(bel.name), "name")
bba.u32(bel_types[ddrg.to_str(bel.type)], "type")
+ bba.u32(bel.z, "z")
bba.u32(len(bel.wires), "num_bel_wires")
bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires")