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| author | gatecat <gatecat@ds0.me> | 2021-06-10 13:10:29 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-06-10 13:10:29 +0100 |
| commit | e9d5b75d1d9333d359e576508235c7e35002b1c8 (patch) | |
| tree | c5c5ac59588312f8ff18294eee7a30c163b3f269 | |
| parent | 13c037cc0847d8eea94dabf719ca17dad69254c9 (diff) | |
| download | nextpnr-e9d5b75d1d9333d359e576508235c7e35002b1c8.tar.gz nextpnr-e9d5b75d1d9333d359e576508235c7e35002b1c8.tar.bz2 nextpnr-e9d5b75d1d9333d359e576508235c7e35002b1c8.zip | |
ecp5: Add missing clock edge assignments
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | ecp5/arch.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index ae9d1af0..aed7cf20 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -1067,6 +1067,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port } } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { info.clock_port = id_CLK; + info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { info.clockToQ = DelayQuad(getDelayFromNS(0.5)); } else { @@ -1075,6 +1076,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port } } else if (cell->type == id_DQSBUFM) { info.clock_port = id_SCLK; + info.edge = RISING_EDGE; if (port == id_DATAVALID) { info.clockToQ = DelayQuad(getDelayFromNS(0.2)); } else if (port == id_READ0 || port == id_READ1) { |