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author | gatecat <gatecat@ds0.me> | 2021-04-30 11:07:14 +0100 |
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committer | gatecat <gatecat@ds0.me> | 2021-04-30 11:07:14 +0100 |
commit | ecf24201ec35c01045a970cff4ed471f1b23a19b (patch) | |
tree | 70f07235f5cc536b3089b29d8d4027f29b809983 | |
parent | d718ccaa78763300146f0b8e5f2339b7fba97542 (diff) | |
download | nextpnr-ecf24201ec35c01045a970cff4ed471f1b23a19b.tar.gz nextpnr-ecf24201ec35c01045a970cff4ed471f1b23a19b.tar.bz2 nextpnr-ecf24201ec35c01045a970cff4ed471f1b23a19b.zip |
interchange: Add wire types to chipdb
Signed-off-by: gatecat <gatecat@ds0.me>
-rw-r--r-- | fpga_interchange/chipdb.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index b66640e3..e9cac84e 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 7; +static constexpr int32_t kExpectedChipInfoVersion = 8; // Flattened site indexing. // @@ -182,6 +182,9 @@ NPNR_PACKED_STRUCT(struct TileInstInfoPOD { // as they will never be nodal // -1 if a tile-local wire; node index if nodal wire RelSlice<int32_t> tile_wire_to_node; + + // Index into wire_types + RelSlice<int16_t> tile_wire_to_type; }); NPNR_PACKED_STRUCT(struct TileWireRefPOD { @@ -305,6 +308,18 @@ NPNR_PACKED_STRUCT(struct ConstantsPOD { RelSlice<DefaultCellConnsPOD> default_conns; }); +enum WireCategory +{ + WIRE_CAT_GENERAL = 0, + WIRE_CAT_SPECIAL = 1, + WIRE_CAT_GLOBAL = 2, +}; + +NPNR_PACKED_STRUCT(struct WireTypePOD { + int32_t name; // constid + int32_t category; // WireCategory +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr<char> name; RelPtr<char> generator; @@ -317,6 +332,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelSlice<TileInstInfoPOD> tiles; RelSlice<NodeInfoPOD> nodes; RelSlice<PackagePOD> packages; + RelSlice<WireTypePOD> wire_types; // BEL bucket constids. RelSlice<int32_t> bel_buckets; |