nexus: Add support for initialised LRAM

Signed-off-by: David Shah <dave@ds0.me>

4 files changed, 50 insertions, 12 deletions

diff --git a/nexus/arch.h b/nexus/arch.h
index c1a5fcde..7ed0b8c3 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -847,9 +847,10 @@ enum CellPinStyle
     PINSTYLE_PU = 0x4022,   // signals that float high and default high
     PINSTYLE_T = 0x4027,    // PIO 'T' signal
 
-    PINSTYLE_ADLSB = 0x4017,  // special case of the EBR address MSBs
-    PINSTYLE_INV_PD = 0x0017, // invertible, pull down by default
-    PINSTYLE_INV_PU = 0x4027, // invertible, pull up by default
+    PINSTYLE_ADLSB = 0x4017,      // special case of the EBR address MSBs
+    PINSTYLE_INV_PD = 0x0017,     // invertible, pull down by default
+    PINSTYLE_INV_PD_CIB = 0x4017, // invertible, pull down by default
+    PINSTYLE_INV_PU = 0x4027,     // invertible, pull up by default
 
     PINSTYLE_IOL_CE = 0x2027, // CE type signal, with explicit 'const-1' config bit
     PINSTYLE_GATE = 0x1011,   // gated signal that defaults to 0
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 0c53e836..b041bf43 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -603,7 +603,7 @@ struct NexusFasmWriter
         push_bel(bel);
         write_enum(cell, "ASYNC_RST_RELEASE", "SYNC");
         write_enum(cell, "EBR_SP_EN", "DISABLE");
-        write_enum(cell, "ECC_BYTE_SEL", "ECC_EN");
+        write_enum(cell, "ECC_BYTE_SEL", "BYTE_EN");
         write_enum(cell, "GSR", "DISABLED");
         write_enum(cell, "OUT_REGMODE_A", "NO_REG");
         write_enum(cell, "OUT_REGMODE_B", "NO_REG");
@@ -611,6 +611,28 @@ struct NexusFasmWriter
         write_enum(cell, "UNALIGNED_READ", "DISABLE");
         write_cell_muxes(cell);
         pop();
+        blank();
+
+        Loc l = ctx->getBelLocation(bel);
+        push(stringf("IP_LRAM_CORE_R%dC%d", l.y, l.x));
+        for (int i = 0; i < 128; i++) {
+            IdString param = ctx->id(stringf("INITVAL_%02X", i));
+            if (!cell->params.count(param))
+                continue;
+            auto &prop = cell->params.at(param);
+            std::string value;
+            if (prop.is_string) {
+                NPNR_ASSERT(prop.str.substr(0, 2) == "0x");
+                // Lattice-style hex string
+                value = prop.str.substr(2);
+                value = stringf("5120'h%s", value.c_str());
+            } else {
+                // True Verilog bitvector
+                value = stringf("5120'b%s", prop.str.c_str());
+            }
+            write_bit(stringf("INITVAL_%02X[5119:0] = %s", i, value.c_str()));
+        }
+        pop();
     }
     // Write out FASM for unused bels where needed
     void write_unused()
diff --git a/nexus/pack.cc b/nexus/pack.cc
index b1642153..9bb90592 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1132,14 +1132,17 @@ struct NexusPacker
             CellInfo *ci = cell.second;
             if (ci->type != id_LRAM_CORE)
                 continue;
+            if (str_or_default(ci->params, ctx->id("ECC_BYTE_SEL"), "BYTE_EN") == "BYTE_EN")
+                continue;
             for (int i = 0; i < 0x80; i++) {
-                // FIXME: support on the prjoxide side
+                // FIXME: document ECC and remove this DRC
                 std::string name = stringf("INITVAL_%02X", i);
                 if (!ci->params.count(ctx->id(name)))
                     continue;
                 if (ci->params.at(ctx->id(name)).str.find_last_not_of("0x") == std::string::npos)
                     continue;
-                log_error("LRAM initialisation is currently unsupported (prjoxide limitation).\n");
+                log_error("LRAM initialisation is currently unsupported in ECC mode (to disable ECC, set ECC_BYTE_SEL "
+                          "to BYTE_EN).\n");
             }
         }
     }
diff --git a/nexus/pins.cc b/nexus/pins.cc
index 5586aeea..b6f2a347 100644
--- a/nexus/pins.cc
+++ b/nexus/pins.cc
@@ -170,12 +170,24 @@ static const std::unordered_map<IdString, Arch::CellPinsData> base_cell_pin_data
          }},
         {id_LRAM_CORE,
          {
-                 {id_CLK, PINSTYLE_CLK},      {id_CEA, PINSTYLE_CE},       {id_CEB, PINSTYLE_CE},
-                 {id_OCEA, PINSTYLE_PU},      {id_OCEB, PINSTYLE_PU},      {id_CSA, PINSTYLE_CE},
-                 {id_CSB, PINSTYLE_CE},       {id_RSTA, PINSTYLE_LSR},     {id_RSTB, PINSTYLE_LSR},
-                 {id_WEA, PINSTYLE_LSR},      {id_WEB, PINSTYLE_LSR},      {id_IGN, PINSTYLE_PU},
-                 {id_INITN, PINSTYLE_PU},     {id_STDBYN, PINSTYLE_PU},    {id_TBISTN, PINSTYLE_PU},
-                 {id_SCANCLK, PINSTYLE_DEDI}, {id_SCANRST, PINSTYLE_DEDI}, {id_OPCGLDCK, PINSTYLE_DEDI},
+                 {id_CLK, PINSTYLE_CLK},
+                 {id_CEA, PINSTYLE_CE},
+                 {id_CEB, PINSTYLE_CE},
+                 {id_OCEA, PINSTYLE_PU},
+                 {id_OCEB, PINSTYLE_PU},
+                 {id_CSA, PINSTYLE_PU},
+                 {id_CSB, PINSTYLE_PU},
+                 {id_RSTA, PINSTYLE_LSR},
+                 {id_RSTB, PINSTYLE_LSR},
+                 {id_WEA, PINSTYLE_INV_PD_CIB},
+                 {id_WEB, PINSTYLE_INV_PD_CIB},
+                 {id_IGN, PINSTYLE_PU},
+                 {id_INITN, PINSTYLE_PU},
+                 {id_STDBYN, PINSTYLE_PU},
+                 {id_TBISTN, PINSTYLE_PU},
+                 {id_SCANCLK, PINSTYLE_DEDI},
+                 {id_SCANRST, PINSTYLE_DEDI},
+                 {id_OPCGLDCK, PINSTYLE_DEDI},
                  {{}, PINSTYLE_CIB},
          }}};
 } // namespace