Merge pull request #1019 from antmicro/support-clock-relations

Support cross-domain clock relations in timing analyser

1 files changed, 5 insertions, 0 deletions

diff --git a/common/kernel/command.cc b/common/kernel/command.cc
index 00f900b3..c548509f 100644
--- a/common/kernel/command.cc
+++ b/common/kernel/command.cc
@@ -172,6 +172,7 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("no-pack", "process design without packing");
 
     general.add_options()("ignore-loops", "ignore combinational loops in timing analysis");
+    general.add_options()("ignore-rel-clk", "ignore clock-to-clock relations in timing checks");
 
     general.add_options()("version,V", "show version");
     general.add_options()("test", "check architecture database integrity");
@@ -270,6 +271,10 @@ void CommandHandler::setupContext(Context *ctx)
         ctx->settings[ctx->id("timing/ignoreLoops")] = true;
     }
 
+    if (vm.count("ignore-rel-clk")) {
+        ctx->settings[ctx->id("timing/ignoreRelClk")] = true;
+    }
+
     if (vm.count("timing-allow-fail")) {
         ctx->settings[ctx->id("timing/allowFail")] = true;
     }