diff options
| author | gatecat <gatecat@ds0.me> | 2021-02-15 09:38:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-15 09:38:22 +0000 |
| commit | 1b6cdce9251d42236a3db0314e84d6a3e3f06408 (patch) | |
| tree | be3b382420edd6cb1f1b6203f7ac518c7aeb4a4f /common/timing.cc | |
| parent | f1ccc0e20531f63355e3da7c6c5f4f39a684fa3f (diff) | |
| parent | 7c7d69e1d2030dc983d0ddbc0e04f6765d51bbbc (diff) | |
| download | nextpnr-1b6cdce9251d42236a3db0314e84d6a3e3f06408.tar.gz nextpnr-1b6cdce9251d42236a3db0314e84d6a3e3f06408.tar.bz2 nextpnr-1b6cdce9251d42236a3db0314e84d6a3e3f06408.zip | |
Merge pull request #575 from YosysHQ/gatecat/belpin-2
Support for cell pin to bel pin mappings
Diffstat (limited to 'common/timing.cc')
| -rw-r--r-- | common/timing.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/common/timing.cc b/common/timing.cc index 9fb14a33..a741c6ee 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -869,7 +869,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx)); if (ctx->verbose) { auto driver_wire = ctx->getNetinfoSourceWire(net); - auto sink_wire = ctx->getNetinfoSinkWire(net, *sink); + auto sink_wire = ctx->getNetinfoSinkWire(net, *sink, 0); log_info(" prediction: %f ns estimate: %f ns\n", ctx->getDelayNS(ctx->predictDelay(net, *sink)), ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire))); |