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authorgatecat <gatecat@ds0.me>2021-02-10 12:28:40 +0000
committergatecat <gatecat@ds0.me>2021-02-10 14:18:12 +0000
commit535723f414a77eb4aa43b794627bbd4aca56f6f0 (patch)
treead130cb32c2b6ff29de73d88d12bdbfe0ed2fd66 /common/timing.cc
parent85bb108ba40f9573571de0a785f9fbc91c4e1dd0 (diff)
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Start making use of getBelPinsForCellPin API
This replaces getNetinfoSinkWire with 3 new functions for different use cases. At the moment all existing code has been moved to getNetinfoSinkWire with phys_idx=0 so the build doesn't break; but this won't yet function properly with more than one sink. But it provides a base on which to work on refactoring the routers to support this case. Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'common/timing.cc')
-rw-r--r--common/timing.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/common/timing.cc b/common/timing.cc
index 9fb14a33..a741c6ee 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -869,7 +869,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
if (ctx->verbose) {
auto driver_wire = ctx->getNetinfoSourceWire(net);
- auto sink_wire = ctx->getNetinfoSinkWire(net, *sink);
+ auto sink_wire = ctx->getNetinfoSinkWire(net, *sink, 0);
log_info(" prediction: %f ns estimate: %f ns\n",
ctx->getDelayNS(ctx->predictDelay(net, *sink)),
ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));