Rename Design to Context, derive from Arch instead of instantiating

Signed-off-by: Clifford Wolf <clifford@clifford.at>

9 files changed, 123 insertions, 132 deletions

diff --git a/common/design.h b/common/design.h
index 13c66d4e..cae50904 100644
--- a/common/design.h
+++ b/common/design.h
@@ -70,17 +70,15 @@ struct CellInfo
     std::unordered_map<IdString, IdString> pins;
 };
 
-struct Design
+struct Context : Arch
 {
-    struct Arch chip;
+    std::unordered_map<IdString, NetInfo *> nets;
+    std::unordered_map<IdString, CellInfo *> cells;
 
-    Design(ArchArgs args) : chip(args)
+    Context(ArchArgs args) : Arch(args)
     {
         // ...
     }
-
-    std::unordered_map<IdString, NetInfo *> nets;
-    std::unordered_map<IdString, CellInfo *> cells;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/common/design_utils.cc b/common/design_utils.cc
index ae6e21ed..f2ce2285 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -53,16 +53,16 @@ void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
 }
 
 // Print utilisation of a design
-void print_utilisation(const Design *design)
+void print_utilisation(const Context *ctx)
 {
     // Sort by Bel type
     std::map<BelType, int> used_types;
-    for (auto cell : design->cells) {
+    for (auto cell : ctx->cells) {
         used_types[belTypeFromId(cell.second->type)]++;
     }
     std::map<BelType, int> available_types;
-    for (auto bel : design->chip.getBels()) {
-        available_types[design->chip.getBelType(bel)]++;
+    for (auto bel : ctx->getBels()) {
+        available_types[ctx->getBelType(bel)]++;
     }
     log("\nDesign utilisation:\n");
     for (auto type : available_types) {
diff --git a/common/design_utils.h b/common/design_utils.h
index d640bf68..2177c0e5 100644
--- a/common/design_utils.h
+++ b/common/design_utils.h
@@ -84,7 +84,7 @@ CellInfo *net_driven_by(const NetInfo *net, F1 cell_pred, IdString port)
     }
 }
 
-void print_utilisation(const Design *design);
+void print_utilisation(const Context *ctx);
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/common/place_sa.cc b/common/place_sa.cc
index f1c3dea2..19588d27 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -70,7 +70,7 @@ static int random_int_between(rnd_state &rnd, int a, int b)
 }
 
 // Initial random placement
-static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
+static void place_initial(Context *ctx, CellInfo *cell, rnd_state &rnd)
 {
     bool all_placed = false;
     int iters = 25;
@@ -78,18 +78,17 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
         BelId best_bel = BelId();
         float best_score = std::numeric_limits<float>::infinity(),
               best_ripup_score = std::numeric_limits<float>::infinity();
-        Arch &chip = design->chip;
         CellInfo *ripup_target = nullptr;
         BelId ripup_bel = BelId();
         if (cell->bel != BelId()) {
-            chip.unbindBel(cell->bel);
+            ctx->unbindBel(cell->bel);
             cell->bel = BelId();
         }
         BelType targetType = belTypeFromId(cell->type);
-        for (auto bel : chip.getBels()) {
-            if (chip.getBelType(bel) == targetType &&
-                isValidBelForCell(design, cell, bel)) {
-                if (chip.checkBelAvail(bel)) {
+        for (auto bel : ctx->getBels()) {
+            if (ctx->getBelType(bel) == targetType &&
+                isValidBelForCell(ctx, cell, bel)) {
+                if (ctx->checkBelAvail(bel)) {
                     float score = random_float_upto(rnd, 1.0);
                     if (score <= best_score) {
                         best_score = score;
@@ -100,7 +99,7 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
                     if (score <= best_ripup_score) {
                         best_ripup_score = score;
                         ripup_target =
-                                design->cells.at(chip.getBelCell(bel, true));
+                                ctx->cells.at(ctx->getBelCell(bel, true));
                         ripup_bel = bel;
                     }
                 }
@@ -111,17 +110,17 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
                 log_error("failed to place cell '%s' of type '%s'\n",
                           cell->name.c_str(), cell->type.c_str());
             --iters;
-            chip.unbindBel(ripup_target->bel);
+            ctx->unbindBel(ripup_target->bel);
             ripup_target->bel = BelId();
             best_bel = ripup_bel;
         } else {
             all_placed = true;
         }
         cell->bel = best_bel;
-        chip.bindBel(cell->bel, cell->name);
+        ctx->bindBel(cell->bel, cell->name);
 
         // Back annotate location
-        cell->attrs["BEL"] = chip.getBelName(cell->bel).str();
+        cell->attrs["BEL"] = ctx->getBelName(cell->bel).str();
         cell = ripup_target;
     }
 }
@@ -174,22 +173,21 @@ static float get_wirelength(Arch *chip, NetInfo *net)
 }
 
 // Attempt a SA position swap, return true on success or false on failure
-static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
+static bool try_swap_position(Context *ctx, CellInfo *cell, BelId newBel,
                               rnd_state &rnd, SAState &state)
 {
     static std::unordered_set<NetInfo *> update;
     static std::vector<std::pair<NetInfo *, float>> new_lengths;
     new_lengths.clear();
     update.clear();
-    Arch &chip = design->chip;
     BelId oldBel = cell->bel;
-    IdString other = chip.getBelCell(newBel, true);
+    IdString other = ctx->getBelCell(newBel, true);
     CellInfo *other_cell = nullptr;
     float new_wirelength = 0, delta;
-    chip.unbindBel(oldBel);
+    ctx->unbindBel(oldBel);
     if (other != IdString()) {
-        other_cell = design->cells[other];
-        chip.unbindBel(newBel);
+        other_cell = ctx->cells[other];
+        ctx->unbindBel(newBel);
     }
 
     for (const auto &port : cell->ports)
@@ -202,17 +200,17 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
                 update.insert(port.second.net);
     }
 
-    chip.bindBel(newBel, cell->name);
+    ctx->bindBel(newBel, cell->name);
 
     if (other != IdString()) {
-        chip.bindBel(oldBel, other_cell->name);
+        ctx->bindBel(oldBel, other_cell->name);
     }
 
-    if (!isBelLocationValid(design, newBel) ||
-        ((other != IdString() && !isBelLocationValid(design, oldBel)))) {
-        chip.unbindBel(newBel);
+    if (!isBelLocationValid(ctx, newBel) ||
+        ((other != IdString() && !isBelLocationValid(ctx, oldBel)))) {
+        ctx->unbindBel(newBel);
         if (other != IdString())
-            chip.unbindBel(oldBel);
+            ctx->unbindBel(oldBel);
         goto swap_fail;
     }
 
@@ -225,7 +223,7 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
     // Recalculate wirelengths for all nets touched by the peturbation
     for (auto net : update) {
         new_wirelength -= state.wirelengths.at(net);
-        float net_new_wl = get_wirelength(&chip, net);
+        float net_new_wl = get_wirelength(ctx, net);
         new_wirelength += net_new_wl;
         new_lengths.push_back(std::make_pair(net, net_new_wl));
     }
@@ -240,8 +238,8 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
             state.improved = true;
     } else {
         if (other != IdString())
-            chip.unbindBel(oldBel);
-        chip.unbindBel(newBel);
+            ctx->unbindBel(oldBel);
+        ctx->unbindBel(newBel);
         goto swap_fail;
     }
     state.curr_wirelength = new_wirelength;
@@ -250,10 +248,10 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
 
     return true;
 swap_fail:
-    chip.bindBel(oldBel, cell->name);
+    ctx->bindBel(oldBel, cell->name);
     cell->bel = oldBel;
     if (other != IdString()) {
-        chip.bindBel(newBel, other);
+        ctx->bindBel(newBel, other);
         other_cell->bel = newBel;
     }
     return false;
@@ -261,13 +259,12 @@ swap_fail:
 
 // Find a random Bel of the correct type for a cell, within the specified
 // diameter
-BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
+BelId random_bel_for_cell(Context *ctx, CellInfo *cell, SAState &state,
                           rnd_state &rnd)
 {
-    Arch &chip = design->chip;
     BelType targetType = belTypeFromId(cell->type);
     int x = 0, y = 0;
-    chip.estimatePosition(cell->bel, x, y);
+    ctx->estimatePosition(cell->bel, x, y);
     while (true) {
         int nx = random_int_between(rnd, std::max(int(x) - state.diameter, 0),
                                     int(x) + state.diameter + 1);
@@ -288,26 +285,26 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
     }
 }
 
-void place_design_sa(Design *design, int seed)
+void place_design_sa(Context *ctx, int seed)
 {
     SAState state;
 
     size_t placed_cells = 0;
     std::queue<CellInfo *> visit_cells;
     // Initial constraints placer
-    for (auto cell_entry : design->cells) {
+    for (auto cell_entry : ctx->cells) {
         CellInfo *cell = cell_entry.second;
         auto loc = cell->attrs.find("BEL");
         if (loc != cell->attrs.end()) {
             std::string loc_name = loc->second;
-            BelId bel = design->chip.getBelByName(IdString(loc_name));
+            BelId bel = ctx->getBelByName(IdString(loc_name));
             if (bel == BelId()) {
                 log_error("No Bel named \'%s\' located for "
                           "this chip (processing BEL attribute on \'%s\')\n",
                           loc_name.c_str(), cell->name.c_str());
             }
 
-            BelType bel_type = design->chip.getBelType(bel);
+            BelType bel_type = ctx->getBelType(bel);
             if (bel_type != belTypeFromId(cell->type)) {
                 log_error("Bel \'%s\' of type \'%s\' does not match cell "
                           "\'%s\' of type \'%s\'",
@@ -316,7 +313,7 @@ void place_design_sa(Design *design, int seed)
             }
 
             cell->bel = bel;
-            design->chip.bindBel(bel, cell->name);
+            ctx->bindBel(bel, cell->name);
             state.locked_bels.insert(bel);
             placed_cells++;
             visit_cells.push(cell);
@@ -327,7 +324,7 @@ void place_design_sa(Design *design, int seed)
     rnd.state = seed;
     std::vector<CellInfo *> autoplaced;
     // Sort to-place cells for deterministic initial placement
-    for (auto cell : design->cells) {
+    for (auto cell : ctx->cells) {
         CellInfo *ci = cell.second;
         if (ci->bel == BelId()) {
             autoplaced.push_back(cell.second);
@@ -337,16 +334,16 @@ void place_design_sa(Design *design, int seed)
               [](CellInfo *a, CellInfo *b) { return a->name < b->name; });
     // Place cells randomly initially
     for (auto cell : autoplaced) {
-        place_initial(design, cell, rnd);
+        place_initial(ctx, cell, rnd);
         placed_cells++;
     }
     // Build up a fast position/type to Bel lookup table
     int max_x = 0, max_y = 0;
     int bel_types = 0;
-    for (auto bel : design->chip.getBels()) {
+    for (auto bel : ctx->getBels()) {
         int x, y;
-        design->chip.estimatePosition(bel, x, y);
-        BelType type = design->chip.getBelType(bel);
+        ctx->estimatePosition(bel, x, y);
+        BelType type = ctx->getBelType(bel);
         int type_idx;
         if (state.bel_types.find(type) == state.bel_types.end()) {
             type_idx = bel_types++;
@@ -367,8 +364,8 @@ void place_design_sa(Design *design, int seed)
     state.diameter = std::max(max_x, max_y) + 1;
     // Calculate wirelength after initial placement
     state.curr_wirelength = 0;
-    for (auto net : design->nets) {
-        float wl = get_wirelength(&design->chip, net.second);
+    for (auto net : ctx->nets) {
+        float wl = get_wirelength(ctx, net.second);
         state.wirelengths[net.second] = wl;
         state.curr_wirelength += wl;
     }
@@ -390,11 +387,11 @@ void place_design_sa(Design *design, int seed)
             // Loop through all automatically placed cells
             for (auto cell : autoplaced) {
                 // Find another random Bel for this cell
-                BelId try_bel = random_bel_for_cell(design, cell, state, rnd);
+                BelId try_bel = random_bel_for_cell(ctx, cell, state, rnd);
                 // If valid, try and swap to a new position and see if
                 // the new position is valid/worthwhile
                 if (try_bel != BelId() && try_bel != cell->bel)
-                    try_swap_position(design, cell, try_bel, rnd, state);
+                    try_swap_position(ctx, cell, try_bel, rnd, state);
             }
         }
         // Heuristic to improve placement on the 8k
@@ -434,14 +431,14 @@ void place_design_sa(Design *design, int seed)
             }
         }
     }
-    for (auto bel : design->chip.getBels()) {
-        if (!isBelLocationValid(design, bel)) {
+    for (auto bel : ctx->getBels()) {
+        if (!isBelLocationValid(ctx, bel)) {
             std::string cell_text = "no cell";
-            IdString cell = design->chip.getBelCell(bel, false);
+            IdString cell = ctx->getBelCell(bel, false);
             if (cell != IdString())
                 cell_text = std::string("cell '") + cell.str() + "'";
             log_error("post-placement validity check failed for Bel '%s' (%s)",
-                      design->chip.getBelName(bel).c_str(), cell_text.c_str());
+                      ctx->getBelName(bel).c_str(), cell_text.c_str());
         }
     }
 }
diff --git a/common/place_sa.h b/common/place_sa.h
index 944cb97e..8ac9e8f6 100644
--- a/common/place_sa.h
+++ b/common/place_sa.h
@@ -23,7 +23,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-extern void place_design_sa(Design *design, int seed);
+extern void place_design_sa(Context *ctx, int seed);
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/common/pybindings.cc b/common/pybindings.cc
index 3621d27a..4c10939a 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -47,7 +47,7 @@ bool operator==(const PortRef &a, const PortRef &b)
 }
 
 // Load a JSON file into a design
-void parse_json_shim(std::string filename, Design &d)
+void parse_json_shim(std::string filename, Context &d)
 {
     std::ifstream inf(filename);
     if (!inf)
@@ -57,9 +57,9 @@ void parse_json_shim(std::string filename, Design &d)
 }
 
 // Create a new Chip and load design from json file
-Design load_design_shim(std::string filename, ArchArgs args)
+Context load_design_shim(std::string filename, ArchArgs args)
 {
-    Design d(args);
+    Context d(args);
     parse_json_shim(filename, d);
     return d;
 }
@@ -113,13 +113,12 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
     WRAP_MAP(decltype(CellInfo::ports), "IdPortMap");
     // WRAP_MAP(decltype(CellInfo::pins), "IdIdMap");
 
-    class_<Design, Design *>("Design", no_init)
-            .def_readwrite("chip", &Design::chip)
-            .def_readwrite("nets", &Design::nets)
-            .def_readwrite("cells", &Design::cells);
+    class_<Context, Context *>("Context", no_init)
+            .def_readwrite("nets", &Context::nets)
+            .def_readwrite("cells", &Context::cells);
 
-    WRAP_MAP(decltype(Design::nets), "IdNetMap");
-    WRAP_MAP(decltype(Design::cells), "IdCellMap");
+    WRAP_MAP(decltype(Context::nets), "IdNetMap");
+    WRAP_MAP(decltype(Context::cells), "IdCellMap");
 
     def("parse_json", parse_json_shim);
     def("load_design", load_design_shim);
diff --git a/common/route.cc b/common/route.cc
index a4127532..080440d6 100644
--- a/common/route.cc
+++ b/common/route.cc
@@ -44,15 +44,14 @@ struct QueuedWire
     };
 };
 
-void ripup_net(Design *design, IdString net_name)
+void ripup_net(Context *ctx, IdString net_name)
 {
-    auto &chip = design->chip;
-    auto net_info = design->nets.at(net_name);
+    auto net_info = ctx->nets.at(net_name);
 
     for (auto &it : net_info->wires) {
         if (it.second != PipId())
-            chip.unbindPip(it.second);
-        chip.unbindWire(it.first);
+            ctx->unbindPip(it.second);
+        ctx->unbindWire(it.first);
     }
 
     net_info->wires.clear();
@@ -66,11 +65,10 @@ struct Router
     delay_t maxDelay = 0.0;
     WireId failedDest;
 
-    Router(Design *design, IdString net_name, bool verbose, bool ripup = false,
+    Router(Context *ctx, IdString net_name, bool verbose, bool ripup = false,
            delay_t ripup_penalty = 0)
     {
-        auto &chip = design->chip;
-        auto net_info = design->nets.at(net_name);
+        auto net_info = ctx->nets.at(net_name);
 
         if (verbose)
             log("Routing net %s.\n", net_name.c_str());
@@ -87,7 +85,7 @@ struct Router
                       net_info->driver.cell->type.c_str());
 
         if (verbose)
-            log("    Source bel: %s\n", chip.getBelName(src_bel).c_str());
+            log("    Source bel: %s\n", ctx->getBelName(src_bel).c_str());
 
         IdString driver_port = net_info->driver.port;
 
@@ -95,22 +93,22 @@ struct Router
         if (driver_port_it != net_info->driver.cell->pins.end())
             driver_port = driver_port_it->second;
 
-        auto src_wire = chip.getWireBelPin(src_bel, portPinFromId(driver_port));
+        auto src_wire = ctx->getWireBelPin(src_bel, portPinFromId(driver_port));
 
         if (src_wire == WireId())
             log_error("No wire found for port %s (pin %s) on source cell %s "
                       "(bel %s).\n",
                       net_info->driver.port.c_str(), driver_port.c_str(),
                       net_info->driver.cell->name.c_str(),
-                      chip.getBelName(src_bel).c_str());
+                      ctx->getBelName(src_bel).c_str());
 
         if (verbose)
-            log("    Source wire: %s\n", chip.getWireName(src_wire).c_str());
+            log("    Source wire: %s\n", ctx->getWireName(src_wire).c_str());
 
         std::unordered_map<WireId, DelayInfo> src_wires;
         src_wires[src_wire] = DelayInfo();
         net_info->wires[src_wire] = PipId();
-        chip.bindWire(src_wire, net_name);
+        ctx->bindWire(src_wire, net_name);
 
         for (auto &user_it : net_info->users) {
             if (verbose)
@@ -126,7 +124,7 @@ struct Router
 
             if (verbose)
                 log("    Destination bel: %s\n",
-                    chip.getBelName(dst_bel).c_str());
+                    ctx->getBelName(dst_bel).c_str());
 
             IdString user_port = user_it.port;
 
@@ -136,20 +134,20 @@ struct Router
                 user_port = user_port_it->second;
 
             auto dst_wire =
-                    chip.getWireBelPin(dst_bel, portPinFromId(user_port));
+                    ctx->getWireBelPin(dst_bel, portPinFromId(user_port));
 
             if (dst_wire == WireId())
                 log_error("No wire found for port %s (pin %s) on destination "
                           "cell %s (bel %s).\n",
                           user_it.port.c_str(), user_port.c_str(),
                           user_it.cell->name.c_str(),
-                          chip.getBelName(dst_bel).c_str());
+                          ctx->getBelName(dst_bel).c_str());
 
             if (verbose) {
                 log("    Destination wire: %s\n",
-                    chip.getWireName(dst_wire).c_str());
+                    ctx->getWireName(dst_wire).c_str());
                 log("    Path delay estimate: %.2f\n",
-                    float(chip.estimateDelay(src_wire, dst_wire)));
+                    float(ctx->estimateDelay(src_wire, dst_wire)));
             }
 
             std::unordered_map<WireId, QueuedWire> visited;
@@ -162,7 +160,7 @@ struct Router
                 qw.wire = it.first;
                 qw.pip = PipId();
                 qw.delay = it.second.avgDelay();
-                qw.togo = chip.estimateDelay(qw.wire, dst_wire);
+                qw.togo = ctx->estimateDelay(qw.wire, dst_wire);
 
                 queue.push(qw);
                 visited[qw.wire] = qw;
@@ -172,26 +170,26 @@ struct Router
                 QueuedWire qw = queue.top();
                 queue.pop();
 
-                for (auto pip : chip.getPipsDownhill(qw.wire)) {
+                for (auto pip : ctx->getPipsDownhill(qw.wire)) {
                     delay_t next_delay = qw.delay;
                     IdString ripupNet = net_name;
                     visitCnt++;
 
-                    if (!chip.checkPipAvail(pip)) {
+                    if (!ctx->checkPipAvail(pip)) {
                         if (!ripup)
                             continue;
-                        ripupNet = chip.getPipNet(pip, true);
+                        ripupNet = ctx->getPipNet(pip, true);
                         if (ripupNet == net_name)
                             continue;
                     }
 
-                    WireId next_wire = chip.getPipDstWire(pip);
-                    next_delay += chip.getPipDelay(pip).avgDelay();
+                    WireId next_wire = ctx->getPipDstWire(pip);
+                    next_delay += ctx->getPipDelay(pip).avgDelay();
 
-                    if (!chip.checkWireAvail(next_wire)) {
+                    if (!ctx->checkWireAvail(next_wire)) {
                         if (!ripup)
                             continue;
-                        ripupNet = chip.getWireNet(next_wire, true);
+                        ripupNet = ctx->getWireNet(next_wire, true);
                         if (ripupNet == net_name)
                             continue;
                     }
@@ -207,7 +205,7 @@ struct Router
                         if (verbose)
                             log("Found better route to %s. Old vs new delay "
                                 "estimate: %.2f %.2f\n",
-                                chip.getWireName(next_wire).c_str(),
+                                ctx->getWireName(next_wire).c_str(),
                                 float(visited.at(next_wire).delay),
                                 float(next_delay));
 #endif
@@ -218,7 +216,7 @@ struct Router
                     next_qw.wire = next_wire;
                     next_qw.pip = pip;
                     next_qw.delay = next_delay;
-                    next_qw.togo = chip.estimateDelay(next_wire, dst_wire);
+                    next_qw.togo = ctx->estimateDelay(next_wire, dst_wire);
                     visited[next_qw.wire] = next_qw;
                     queue.push(next_qw);
                 }
@@ -227,13 +225,13 @@ struct Router
             if (visited.count(dst_wire) == 0) {
                 if (verbose)
                     log("Failed to route %s -> %s.\n",
-                        chip.getWireName(src_wire).c_str(),
-                        chip.getWireName(dst_wire).c_str());
+                        ctx->getWireName(src_wire).c_str(),
+                        ctx->getWireName(dst_wire).c_str());
                 else if (ripup)
                     log_info("Failed to route %s -> %s.\n",
-                             chip.getWireName(src_wire).c_str(),
-                             chip.getWireName(dst_wire).c_str());
-                ripup_net(design, net_name);
+                             ctx->getWireName(src_wire).c_str(),
+                             ctx->getWireName(dst_wire).c_str());
+                ripup_net(ctx, net_name);
                 failedDest = dst_wire;
                 return;
             }
@@ -251,35 +249,35 @@ struct Router
             while (1) {
                 if (verbose)
                     log("    %8.2f %s\n", float(visited[cursor].delay),
-                        chip.getWireName(cursor).c_str());
+                        ctx->getWireName(cursor).c_str());
 
                 if (src_wires.count(cursor))
                     break;
 
-                IdString conflicting_net = chip.getWireNet(cursor, true);
+                IdString conflicting_net = ctx->getWireNet(cursor, true);
 
                 if (conflicting_net != IdString()) {
                     assert(ripup);
                     assert(conflicting_net != net_name);
-                    ripup_net(design, conflicting_net);
+                    ripup_net(ctx, conflicting_net);
                     rippedNets.insert(conflicting_net);
                 }
 
-                conflicting_net = chip.getPipNet(visited[cursor].pip, true);
+                conflicting_net = ctx->getPipNet(visited[cursor].pip, true);
 
                 if (conflicting_net != IdString()) {
                     assert(ripup);
                     assert(conflicting_net != net_name);
-                    ripup_net(design, conflicting_net);
+                    ripup_net(ctx, conflicting_net);
                     rippedNets.insert(conflicting_net);
                 }
 
                 net_info->wires[cursor] = visited[cursor].pip;
-                chip.bindWire(cursor, net_name);
-                chip.bindPip(visited[cursor].pip, net_name);
+                ctx->bindWire(cursor, net_name);
+                ctx->bindPip(visited[cursor].pip, net_name);
 
-                src_wires[cursor] = chip.getPipDelay(visited[cursor].pip);
-                cursor = chip.getPipSrcWire(visited[cursor].pip);
+                src_wires[cursor] = ctx->getPipDelay(visited[cursor].pip);
+                cursor = ctx->getPipSrcWire(visited[cursor].pip);
             }
         }
 
@@ -291,16 +289,15 @@ struct Router
 
 NEXTPNR_NAMESPACE_BEGIN
 
-bool route_design(Design *design, bool verbose)
+bool route_design(Context *ctx, bool verbose)
 {
-    auto &chip = design->chip;
     delay_t ripup_penalty = 5;
 
     log_info("Routing..\n");
 
     std::unordered_set<IdString> netsQueue;
 
-    for (auto &net_it : design->nets) {
+    for (auto &net_it : ctx->nets) {
         auto net_name = net_it.first;
         auto net_info = net_it.second;
 
@@ -325,7 +322,7 @@ bool route_design(Design *design, bool verbose)
     int estimatedTotalDelayCnt = 0;
 
     for (auto net_name : netsQueue) {
-        auto net_info = design->nets.at(net_name);
+        auto net_info = ctx->nets.at(net_name);
 
         auto src_bel = net_info->driver.cell->bel;
 
@@ -338,7 +335,7 @@ bool route_design(Design *design, bool verbose)
         if (driver_port_it != net_info->driver.cell->pins.end())
             driver_port = driver_port_it->second;
 
-        auto src_wire = chip.getWireBelPin(src_bel, portPinFromId(driver_port));
+        auto src_wire = ctx->getWireBelPin(src_bel, portPinFromId(driver_port));
 
         if (src_wire == WireId())
             continue;
@@ -357,12 +354,12 @@ bool route_design(Design *design, bool verbose)
                 user_port = user_port_it->second;
 
             auto dst_wire =
-                    chip.getWireBelPin(dst_bel, portPinFromId(user_port));
+                    ctx->getWireBelPin(dst_bel, portPinFromId(user_port));
 
             if (dst_wire == WireId())
                 continue;
 
-            estimatedTotalDelay += chip.estimateDelay(src_wire, dst_wire);
+            estimatedTotalDelay += ctx->estimateDelay(src_wire, dst_wire);
             estimatedTotalDelayCnt++;
         }
     }
@@ -390,9 +387,9 @@ bool route_design(Design *design, bool verbose)
         for (auto net_name : netsQueue) {
             if (printNets)
                 log_info("  routing net %s. (%d users)\n", net_name.c_str(),
-                         int(design->nets.at(net_name)->users.size()));
+                         int(ctx->nets.at(net_name)->users.size()));
 
-            Router router(design, net_name, verbose, false);
+            Router router(ctx, net_name, verbose, false);
 
             netCnt++;
             visitCnt += router.visitCnt;
@@ -401,7 +398,7 @@ bool route_design(Design *design, bool verbose)
             if (!router.routedOkay) {
                 if (printNets)
                     log_info("    failed to route to %s.\n",
-                             chip.getWireName(router.failedDest).c_str());
+                             ctx->getWireName(router.failedDest).c_str());
                 ripupQueue.insert(net_name);
             }
 
@@ -433,9 +430,9 @@ bool route_design(Design *design, bool verbose)
             for (auto net_name : ripupQueue) {
                 if (printNets)
                     log_info("  routing net %s. (%d users)\n", net_name.c_str(),
-                             int(design->nets.at(net_name)->users.size()));
+                             int(ctx->nets.at(net_name)->users.size()));
 
-                Router router(design, net_name, verbose, true,
+                Router router(ctx, net_name, verbose, true,
                               ripup_penalty * (iterCnt - 1));
 
                 netCnt++;
@@ -455,7 +452,7 @@ bool route_design(Design *design, bool verbose)
                                  int(router.rippedNets.size()));
                         for (auto n : router.rippedNets)
                             log_info("      %s (%d users)\n", n.c_str(),
-                                     int(design->nets.at(n)->users.size()));
+                                     int(ctx->nets.at(n)->users.size()));
                     } else {
                         log_info("    ripped up %d other nets.\n",
                                  int(router.rippedNets.size()));
diff --git a/common/route.h b/common/route.h
index fd4368bf..8475957b 100644
--- a/common/route.h
+++ b/common/route.h
@@ -24,7 +24,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-extern bool route_design(Design *design, bool verbose = false);
+extern bool route_design(Context *ctx, bool verbose = false);
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/common/rulecheck.cc b/common/rulecheck.cc
index 987eb602..2f70498f 100644
--- a/common/rulecheck.cc
+++ b/common/rulecheck.cc
@@ -5,13 +5,13 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-bool check_all_nets_driven(Design *design)
+bool check_all_nets_driven(Context *ctx)
 {
     const bool debug = false;
 
     log_info("Rule checker, Verifying pre-placed design\n");
 
-    for (auto cell_entry : design->cells) {
+    for (auto cell_entry : ctx->cells) {
         CellInfo *cell = cell_entry.second;
 
         if (debug)
@@ -37,12 +37,12 @@ bool check_all_nets_driven(Design *design)
                 if (debug)
                     log_info("    Checking for a net named \'%s\'\n",
                              port.net->name.c_str());
-                assert(design->nets.count(port.net->name) > 0);
+                assert(ctx->nets.count(port.net->name) > 0);
             }
         }
     }
 
-    for (auto net_entry : design->nets) {
+    for (auto net_entry : ctx->nets) {
         NetInfo *net = net_entry.second;
 
         assert(net->name == net_entry.first);
@@ -52,7 +52,7 @@ bool check_all_nets_driven(Design *design)
             if (debug)
                 log_info("    Checking for a driver cell named \'%s\'\n",
                          net->driver.cell->name.c_str());
-            assert(design->cells.count(net->driver.cell->name) > 0);
+            assert(ctx->cells.count(net->driver.cell->name) > 0);
         }
 
         for (auto user : net->users) {
@@ -62,7 +62,7 @@ bool check_all_nets_driven(Design *design)
                 if (debug)
                     log_info("    Checking for a user   cell named \'%s\'\n",
                              user.cell->name.c_str());
-                assert(design->cells.count(user.cell->name) > 0);
+                assert(ctx->cells.count(user.cell->name) > 0);
             }
         }
     }