nets and cells are unique_ptr's

8 files changed, 34 insertions, 36 deletions

diff --git a/common/design_utils.cc b/common/design_utils.cc
index 640a18a2..74310ab4 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -56,8 +56,8 @@ void print_utilisation(const Context *ctx)
 {
     // Sort by Bel type
     std::map<BelType, int> used_types;
-    for (auto cell : ctx->cells) {
-        used_types[ctx->belTypeFromId(cell.second->type)]++;
+    for (auto& cell : ctx->cells) {
+        used_types[ctx->belTypeFromId(cell.second.get()->type)]++;
     }
     std::map<BelType, int> available_types;
     for (auto bel : ctx->getBels()) {
diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index 2dc3bacb..a7a3268e 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -163,7 +163,7 @@ uint32_t Context::checksum() const
 void Context::check() const
 {
     for (auto &n : nets) {
-        auto ni = n.second;
+        auto ni = n.second.get();
         assert(n.first == ni->name);
         for (auto &w : ni->wires) {
             assert(n.first == getBoundWireNet(w.first));
diff --git a/common/nextpnr.h b/common/nextpnr.h
index 71a52758..af1ed733 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -24,6 +24,7 @@
 #include <unordered_map>
 #include <unordered_set>
 #include <vector>
+#include <memory>
 
 #ifndef NEXTPNR_H
 #define NEXTPNR_H
@@ -194,8 +195,8 @@ struct BaseCtx
 
     // --------------------------------------------------------------
 
-    std::unordered_map<IdString, NetInfo *> nets;
-    std::unordered_map<IdString, CellInfo *> cells;
+    std::unordered_map<IdString, std::unique_ptr<NetInfo>> nets;
+    std::unordered_map<IdString, std::unique_ptr<CellInfo>> cells;
 
     BaseCtx()
     {
@@ -210,12 +211,6 @@ struct BaseCtx
 
     ~BaseCtx()
     {
-        for (auto &item : nets) {
-            delete item.second;
-        }
-        for (auto &item : cells) {
-            delete item.second;
-        }
         delete idstring_str_to_idx;
         delete idstring_idx_to_str;
     }
diff --git a/common/place_sa.cc b/common/place_sa.cc
index 55496f07..56d92633 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -79,8 +79,8 @@ class SAPlacer
 
         size_t placed_cells = 0;
         // Initial constraints placer
-        for (auto cell_entry : ctx->cells) {
-            CellInfo *cell = cell_entry.second;
+        for (auto& cell_entry : ctx->cells) {
+            CellInfo *cell = cell_entry.second.get();
             auto loc = cell->attrs.find(ctx->id("BEL"));
             if (loc != cell->attrs.end()) {
                 std::string loc_name = loc->second;
@@ -109,10 +109,10 @@ class SAPlacer
 
         // Sort to-place cells for deterministic initial placement
         std::vector<CellInfo *> autoplaced;
-        for (auto cell : ctx->cells) {
-            CellInfo *ci = cell.second;
+        for (auto& cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
             if (ci->bel == BelId()) {
-                autoplaced.push_back(cell.second);
+                autoplaced.push_back(cell.second.get());
             }
         }
         std::sort(autoplaced.begin(), autoplaced.end(), [](CellInfo *a, CellInfo *b) { return a->name < b->name; });
@@ -137,8 +137,8 @@ class SAPlacer
         // Calculate wirelength after initial placement
         curr_wirelength = 0;
         curr_tns = 0;
-        for (auto net : ctx->nets) {
-            wirelen_t wl = get_wirelength(net.second, curr_tns);
+        for (auto& net : ctx->nets) {
+            wirelen_t wl = get_wirelength(net.second.get(), curr_tns);
             wirelengths[net.first] = wl;
             curr_wirelength += wl;
         }
@@ -211,8 +211,8 @@ class SAPlacer
             // accumulating over time
             curr_wirelength = 0;
             curr_tns = 0;
-            for (auto net : ctx->nets) {
-                wirelen_t wl = get_wirelength(net.second, curr_tns);
+            for (auto& net : ctx->nets) {
+                wirelen_t wl = get_wirelength(net.second.get(), curr_tns);
                 wirelengths[net.first] = wl;
                 curr_wirelength += wl;
             }
@@ -266,7 +266,7 @@ class SAPlacer
                         uint64_t score = ctx->rng64();
                         if (score <= best_ripup_score) {
                             best_ripup_score = score;
-                            ripup_target = ctx->cells.at(ctx->getBoundBelCell(bel));
+                            ripup_target = ctx->cells.at(ctx->getBoundBelCell(bel)).get();
                             ripup_bel = bel;
                         }
                     }
@@ -354,7 +354,7 @@ class SAPlacer
         wirelen_t new_wirelength = 0, delta;
         ctx->unbindBel(oldBel);
         if (other != IdString()) {
-            other_cell = ctx->cells[other];
+            other_cell = ctx->cells[other].get();
             ctx->unbindBel(newBel);
         }
 
diff --git a/common/route.cc b/common/route.cc
index a7f8f53f..60965f84 100644
--- a/common/route.cc
+++ b/common/route.cc
@@ -75,7 +75,7 @@ struct RipupScoreboard
 
 void ripup_net(Context *ctx, IdString net_name)
 {
-    auto net_info = ctx->nets.at(net_name);
+    auto net_info = ctx->nets.at(net_name).get();
     std::vector<PipId> pips;
     std::vector<WireId> wires;
 
@@ -249,7 +249,7 @@ struct Router
     Router(Context *ctx, RipupScoreboard &scores, IdString net_name, bool ripup = false, delay_t ripup_penalty = 0)
             : ctx(ctx), scores(scores), net_name(net_name), ripup(ripup), ripup_penalty(ripup_penalty)
     {
-        auto net_info = ctx->nets.at(net_name);
+        auto net_info = ctx->nets.at(net_name).get();
 
         if (ctx->debug)
             log("Routing net %s.\n", net_name.c_str(ctx));
@@ -416,7 +416,7 @@ bool route_design(Context *ctx)
 
         for (auto &net_it : ctx->nets) {
             auto net_name = net_it.first;
-            auto net_info = net_it.second;
+            auto net_info = net_it.second.get();
 
             if (net_info->driver.cell == nullptr)
                 continue;
@@ -438,7 +438,7 @@ bool route_design(Context *ctx)
         int estimatedTotalDelayCnt = 0;
 
         for (auto net_name : netsQueue) {
-            auto net_info = ctx->nets.at(net_name);
+            auto net_info = ctx->nets.at(net_name).get();
 
             auto src_bel = net_info->driver.cell->bel;
 
diff --git a/common/rulecheck.cc b/common/rulecheck.cc
index c27d33ea..d406178a 100644
--- a/common/rulecheck.cc
+++ b/common/rulecheck.cc
@@ -11,8 +11,8 @@ bool check_all_nets_driven(Context *ctx)
 
     log_info("Rule checker, Verifying pre-placed design\n");
 
-    for (auto cell_entry : ctx->cells) {
-        CellInfo *cell = cell_entry.second;
+    for (auto& cell_entry : ctx->cells) {
+        CellInfo *cell = cell_entry.second.get();
 
         if (debug)
             log_info("  Examining cell \'%s\', of type \'%s\'\n", cell->name.c_str(ctx), cell->type.c_str(ctx));
@@ -39,8 +39,8 @@ bool check_all_nets_driven(Context *ctx)
         }
     }
 
-    for (auto net_entry : ctx->nets) {
-        NetInfo *net = net_entry.second;
+    for (auto& net_entry : ctx->nets) {
+        NetInfo *net = net_entry.second.get();
 
         assert(net->name == net_entry.first);
         if ((net->driver.cell != NULL) && (net->driver.cell->type != ctx->id("GND")) &&
diff --git a/common/timing.cc b/common/timing.cc
index 0684c543..5b929c4c 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -76,16 +76,16 @@ void assign_budget(Context *ctx, float default_clock)
     log_info("Annotating ports with timing budgets\n");
     // Clear delays to a very high value first
     delay_t default_slack = delay_t(1.0e12 / default_clock);
-    for (auto net : ctx->nets) {
+    for (auto& net : ctx->nets) {
         for (auto &usr : net.second->users) {
             usr.budget = default_slack;
         }
     }
     // Go through all clocked drivers and set up paths
-    for (auto cell : ctx->cells) {
+    for (auto& cell : ctx->cells) {
         for (auto port : cell.second->ports) {
             if (port.second.type == PORT_OUT) {
-                IdString clock_domain = ctx->getPortClock(cell.second, port.first);
+                IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
                 if (clock_domain != IdString()) {
                     delay_t slack = delay_t(1.0e12 / default_clock); // TODO: clock constraints
                     if (port.second.net)
@@ -96,7 +96,7 @@ void assign_budget(Context *ctx, float default_clock)
     }
 
     // Post-allocation check
-    for (auto net : ctx->nets) {
+    for (auto& net : ctx->nets) {
         for (auto user : net.second->users) {
             if (user.budget < 0)
                 log_warning("port %s.%s, connected to net '%s', has negative "
diff --git a/common/util.h b/common/util.h
index 5e938635..b1cab650 100644
--- a/common/util.h
+++ b/common/util.h
@@ -57,9 +57,12 @@ bool bool_or_default(const Container &ct, const KeyType &key, bool def = false)
 };
 
 // Wrap an unordered_map, and allow it to be iterated over sorted by key
-template <typename K, typename V> std::map<K, V> sorted(const std::unordered_map<K, V> &orig)
+template <typename K, typename V> std::map<K, V*> sorted(const std::unordered_map<K, std::unique_ptr<V>> &orig)
 {
-    return std::map<K, V>(orig.begin(), orig.end());
+    std::map<K, V*> retVal;
+    for(auto& item : orig)
+        retVal.emplace(std::make_pair(item.first,item.second.get()));
+    return retVal;
 };
 
 NEXTPNR_NAMESPACE_END