Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr

2 files changed, 33 insertions, 4 deletions

diff --git a/common/place_sa.cc b/common/place_sa.cc
index 0a60adc8..2b8b960b 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -314,7 +314,12 @@ class SAPlacer
                     load_cell->bel, ctx->portPinFromId(load.port));
             // wirelength += std::abs(load_x - driver_x) + std::abs(load_y -
             // driver_y);
-            wirelength += ctx->estimateDelay(drv_wire, user_wire);
+            delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
+            wirelength += pow(1.3, (ctx->getDelayNS(raw_wl) -
+                                    ctx->getDelayNS(load.budget)) /
+                                           10) +
+                          ctx->getDelayNS(raw_wl);
+            // wirelength += pow(ctx->estimateDelay(drv_wire, user_wire), 2.0);
         }
         return wirelength;
     }
@@ -376,9 +381,8 @@ class SAPlacer
         delta = new_wirelength - curr_wirelength;
         n_move++;
         // SA acceptance criterea
-        if (delta < 0 ||
-            (temp > 1e-6 &&
-             (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
+        if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <=
+                                                 std::exp(-delta / temp))) {
             n_accept++;
             if (delta < 0)
                 improved = true;
diff --git a/common/timing.cc b/common/timing.cc
index 5ffd4ea7..8da26077 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -79,6 +79,14 @@ static delay_t follow_net(Context *ctx, NetInfo *net, int path_length,
 void assign_budget(Context *ctx, float default_clock)
 {
     log_info("Annotating ports with timing budgets\n");
+    // Clear delays to a very high value first
+    delay_t default_slack = delay_t(1.0e12 / default_clock);
+    for (auto net : ctx->nets) {
+        for (auto &usr : net.second->users) {
+            usr.budget = default_slack;
+        }
+    }
+    // Go through all clocked drivers and set up paths
     for (auto cell : ctx->cells) {
         for (auto port : cell.second->ports) {
             if (port.second.type == PORT_OUT) {
@@ -93,6 +101,23 @@ void assign_budget(Context *ctx, float default_clock)
             }
         }
     }
+    const bool debug = true;
+
+    // Post-allocation check
+    for (auto net : ctx->nets) {
+        for (auto user : net.second->users) {
+            if (user.budget < 0)
+                log_warning("port %s.%s, connected to net '%s', has negative "
+                            "timing budget of %fns\n",
+                            user.cell->name.c_str(ctx), user.port.c_str(ctx),
+                            net.first.c_str(ctx), ctx->getDelayNS(user.budget));
+            if (debug)
+                log_warning("port %s.%s, connected to net '%s', has "
+                            "timing budget of %fns\n",
+                            user.cell->name.c_str(ctx), user.port.c_str(ctx),
+                            net.first.c_str(ctx), ctx->getDelayNS(user.budget));
+        }
+    }
 }
 
 NEXTPNR_NAMESPACE_END