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author | David Shah <davey1576@gmail.com> | 2018-11-15 11:26:08 +0000 |
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committer | GitHub <noreply@github.com> | 2018-11-15 11:26:08 +0000 |
commit | 9472b6d78f68544d430feeae6d75dbd2dc43019d (patch) | |
tree | 0ab6b20c90d4a93cd9e2d0c14bdadb296e159cdc /docs/archapi.md | |
parent | d3b2065cd7d2470a132c055f4bd88d270e1e8fe1 (diff) | |
parent | 9f9b242cf0a3b587df8f5b0eb542ca7256ca0eb9 (diff) | |
download | nextpnr-9472b6d78f68544d430feeae6d75dbd2dc43019d.tar.gz nextpnr-9472b6d78f68544d430feeae6d75dbd2dc43019d.tar.bz2 nextpnr-9472b6d78f68544d430feeae6d75dbd2dc43019d.zip |
Merge pull request #103 from YosysHQ/timingapi
Timing constraints API, multiple clock domains
Diffstat (limited to 'docs/archapi.md')
-rw-r--r-- | docs/archapi.md | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/docs/archapi.md b/docs/archapi.md index 40eabd9d..3c938865 100644 --- a/docs/archapi.md +++ b/docs/archapi.md @@ -404,6 +404,10 @@ actual penalty used is a multiple of this value (i.e. a weighted version of this Convert an `delay_t` to an actual real-world delay in nanoseconds. +### DelayInfo getDelayFromNS(float v) const + +Convert a real-world delay in nanoseconds to a DelayInfo with equal min/max rising/falling values. + ### uint32\_t getDelayChecksum(delay\_t v) const Convert a `delay_t` to an integer for checksum calculations. @@ -461,11 +465,17 @@ Cell Delay Methods Returns the delay for the specified path through a cell in the `&delay` argument. The method returns false if there is no timing relationship from `fromPort` to `toPort`. -### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const +### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const Return the _timing port class_ of a port. This can be a register or combinational input or output; clock input or -output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockPort is set -to the associated clock port. +output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockInfoCount is set +to the number of associated _clock edges_ that can be queried by getPortClockingInfo. + +### TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const + +Return the _clocking info_ (including port name of clock, clock polarity and setup/hold/clock-to-out times) of a +port. Where ports have more than one clock edge associated with them (such as DDR outputs), `index` can be used to obtain +information for all edges. `index` must be in [0, clockInfoCount), behaviour is undefined otherwise. Placer Methods -------------- |