Merge pull request #592 from YosysHQ/gatecat/rework-delay

Replace DelayInfo with DelayPair and DelayQuad

2 files changed, 9 insertions, 24 deletions

diff --git a/docs/archapi.md b/docs/archapi.md
index 96d96e80..9ecb1bf1 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -43,21 +43,6 @@ With the exception of `ArchNetInfo` and `ArchCellInfo`, the following types shou
 
 A scalar type that is used to  represent delays. May be an integer or float type.
 
-### DelayInfo
-
-A struct representing the delay across a timing arc. Must provide a `+` operator for getting the combined delay of two arcs, and the following methods to access concrete timings:
-
-```
-delay_t minRaiseDelay() const { return delay; }
-delay_t maxRaiseDelay() const { return delay; }
-
-delay_t minFallDelay() const { return delay; }
-delay_t maxFallDelay() const { return delay; }
-
-delay_t minDelay() const { return delay; }
-delay_t maxDelay() const { return delay; }
-```
-
 ### BelId
 
 A type representing a bel name. `BelId()` must construct a unique null-value. Must provide `==`, `!=`, and `<` operators and a specialization for `std::hash<BelId>`.
@@ -332,7 +317,7 @@ will make the given wire available.
 
 *BaseArch default: returns `getBoundWireNet(wire)`*
 
-### DelayInfo getWireDelay(WireId wire) const
+### DelayQuad getWireDelay(WireId wire) const
 
 Get the delay for a wire.
 
@@ -448,7 +433,7 @@ Get the destination wire for a pip.
 Bi-directional switches (transfer gates) are modeled using two
 anti-parallel pips.
 
-### DelayInfo getPipDelay(PipId pip) const
+### DelayQuad getPipDelay(PipId pip) const
 
 Get the delay for a pip.
 
@@ -541,9 +526,9 @@ actual penalty used is a multiple of this value (i.e. a weighted version of this
 
 Convert an `delay_t` to an actual real-world delay in nanoseconds.
 
-### DelayInfo getDelayFromNS(float v) const
+### delay_t getDelayFromNS(float v) const
 
-Convert a real-world delay in nanoseconds to a DelayInfo with equal min/max rising/falling values.
+Convert a real-world delay in nanoseconds to a `delay_t`.
 
 ### uint32\_t getDelayChecksum(delay\_t v) const
 
@@ -609,7 +594,7 @@ Return the decal and X/Y position for the graphics representing a group.
 Cell Delay Methods
 ------------------
 
-### bool getCellDelay(const CellInfo \*cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+### bool getCellDelay(const CellInfo \*cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 
 Returns the delay for the specified path through a cell in the `&delay` argument. The method returns
 false if there is no timing relationship from `fromPort` to `toPort`.
diff --git a/docs/generic.md b/docs/generic.md
index 5c079a7b..0562bed3 100644
--- a/docs/generic.md
+++ b/docs/generic.md
@@ -22,7 +22,7 @@ so named arguments may be used.
 
 Adds a wire with a name, type (for user purposes only, ignored by all nextpnr code other than the UI) to the FPGA description. x and y give a nominal location of the wire for delay estimation purposes. Delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is not of importance.
 
-### addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
+### addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, float delay, Loc loc);
 
 Adds a pip (programmable connection between two named wires). Pip delays that correspond to delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is otherwise not of importance.
 
@@ -77,16 +77,16 @@ Set the timing class of a port on a particular cell to a clock input.
 _NOTE: All cell timing functions apply to an individual named cell and not a cell type. This is because
 cell-specific configuration might affect timing, e.g. whether or not the register is used for a slice._
 
-### void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
+### void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, float delay);
 
 Specify the combinational delay between two ports of a cell, and set the timing class of
  those ports as combinational input/output.
 
-### void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
+### void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, float setup, float hold);
 
 Specify setup and hold timings for a port of a cell, and set the timing class of that port as register input.
 
-### void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
+### void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, float clktoq);
 
 Specify clock-to-out time for a port of a cell, and set the timing class of that port as register output.