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| author | David Shah <dave@ds0.me> | 2020-10-01 09:02:39 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-10-01 09:02:39 +0100 |
| commit | b5054f0d7777b7f831d2223479628372e968e89a (patch) | |
| tree | 35efc1066ea17131b8336e00b59401f5ba7a85cd /docs | |
| parent | 9aff6aa55c212df448477f3e28711ac3d0ee5aff (diff) | |
| parent | c4244d967d5698ea5932ee7249d8de86eeb3260d (diff) | |
| download | nextpnr-b5054f0d7777b7f831d2223479628372e968e89a.tar.gz nextpnr-b5054f0d7777b7f831d2223479628372e968e89a.tar.bz2 nextpnr-b5054f0d7777b7f831d2223479628372e968e89a.zip | |
Merge branch 'kittennbfive-annotate-primitives' into master
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/constraints.md | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/docs/constraints.md b/docs/constraints.md index 67c8ddd7..dead8780 100644 --- a/docs/constraints.md +++ b/docs/constraints.md @@ -9,11 +9,18 @@ The iCE40 architecture supports PCF constraints thus: set_io led[0] 3 -and the ECP5 architecture supports a subset of LPF constraints: +and the ECP5 architecture supports a subset of LPF constraints (for details see Lattice Technical Note "FPGA-TN-02032 1.3"): LOCATE COMP "led[0]" SITE "E16"; IOBUF PORT "led[0]" IO_TYPE=LVCMOS25; - + IOBUF ... DRIVE=4|8|12|16; // currently LVCMOS33 and LVCMOS33D only + IOBUF ... OPENDRAIN=ON|OFF; + IOBUF ... TERMINATION=50|75|150; + IOBUF ... DIFFRESISTOR=100; //for differential IO only + IOBUF ... CLAMP=ON|OFF; + IOBUF ... PULLMODE=UP|DOWN|NONE; + IOBUF ... SLEWRATE=FAST|SLOW; //outputs only + IOBUF ... HYSTERESIS=ON|OFF; ## Absolute Placement Constraints |