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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-08 19:35:13 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-08-08 19:35:13 +0200 |
| commit | f6189e4677c7bdaeaa5b9b796a67d750e6c7d49d (patch) | |
| tree | a13673a636ddbea3b5fd5585e3bb109b56b69435 /docs | |
| parent | a3ae3f97913c291dbe36a49b1a20388156943abc (diff) | |
| parent | cd4e761bb799ca99f02d3aa177961af28a93f2d8 (diff) | |
| download | nextpnr-f6189e4677c7bdaeaa5b9b796a67d750e6c7d49d.tar.gz nextpnr-f6189e4677c7bdaeaa5b9b796a67d750e6c7d49d.tar.bz2 nextpnr-f6189e4677c7bdaeaa5b9b796a67d750e6c7d49d.zip | |
Merge branch 'master' of github.com:YosysHQ/nextpnr into constids
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/archapi.md | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/docs/archapi.md b/docs/archapi.md index 1ead4c62..df2bc468 100644 --- a/docs/archapi.md +++ b/docs/archapi.md @@ -431,13 +431,11 @@ Cell Delay Methods Returns the delay for the specified path through a cell in the `&delay` argument. The method returns false if there is no timing relationship from `fromPort` to `toPort`. -### IdString getPortClock(const CellInfo \*cell, IdString port) const +### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const -Returns the clock input port for the specified output port. - -### bool isClockPort(const CellInfo \*cell, IdString port) const - -Returns true if the specified port is a clock input. +Return the _timing port class_ of a port. This can be a register or combinational input or output; clock input or +output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockPort is set +to the associated clock port. Placer Methods -------------- |