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author | David Shah <dave@ds0.me> | 2018-11-11 10:46:07 +0000 |
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committer | David Shah <dave@ds0.me> | 2018-11-15 11:30:27 +0000 |
commit | 02736d06800dbbab6eef9d2660e9d481874dd7ae (patch) | |
tree | 0ac5fdd222de110c93e48e6e9e71f4fb35ae317e /ecp5/arch.cc | |
parent | 084f9cf63f148a8af991c5827a25d239709ff0e6 (diff) | |
download | nextpnr-02736d06800dbbab6eef9d2660e9d481874dd7ae.tar.gz nextpnr-02736d06800dbbab6eef9d2660e9d481874dd7ae.tar.bz2 nextpnr-02736d06800dbbab6eef9d2660e9d481874dd7ae.zip |
ecp5: Add timing info for SERDES
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5/arch.cc')
-rw-r--r-- | ecp5/arch.cc | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index a0d8e8ae..afea8d4a 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -652,7 +652,15 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } else if (cell->type == id_EHXPLLL) { return TMG_IGNORE; } else if (cell->type == id_DCUA || cell->type == id_EXTREFB || cell->type == id_PCSCLKDIV) { - return TMG_IGNORE; // FIXME + if (port == id_CH0_FF_TXI_CLK || port == id_CH0_FF_RXI_CLK || port == id_CH1_FF_TXI_CLK || + port == id_CH1_FF_RXI_CLK) + return TMG_CLOCK_INPUT; + std::string prefix = port.str(this).substr(0, 9); + if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") { + clockInfoCount = 1; + return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; + } + return TMG_IGNORE; } else { NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'"); } @@ -708,6 +716,23 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.setup.delay = 100; info.hold.delay = 0; } + } else if (cell->type == id_DCUA) { + std::string prefix = port.str(this).substr(0, 9); + info.edge = RISING_EDGE; + if (prefix == "CH0_FF_TX") + info.clock_port = id_CH0_FF_TXI_CLK; + else if (prefix == "CH0_FF_RX") + info.clock_port = id_CH0_FF_RXI_CLK; + else if (prefix == "CH1_FF_TX") + info.clock_port = id_CH1_FF_TXI_CLK; + else if (prefix == "CH1_FF_RX") + info.clock_port = id_CH1_FF_RXI_CLK; + if (cell->ports.at(port).type == PORT_OUT) { + info.clockToQ.delay = 660; + } else { + info.setup.delay = 1000; + info.hold.delay = 0; + } } return info; } |