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author | gatecat <gatecat@ds0.me> | 2021-07-06 11:45:27 +0100 |
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committer | gatecat <gatecat@ds0.me> | 2021-07-06 11:45:37 +0100 |
commit | 81c549549d88640ed77fc2b1f3da52a10b4f93ce (patch) | |
tree | 76a618926561d9cb1ae2e3b13cf588731514736d /ecp5/arch.cc | |
parent | 8a9fb810369aeb5eed128ef4e7d4de456ef1ec8f (diff) | |
download | nextpnr-81c549549d88640ed77fc2b1f3da52a10b4f93ce.tar.gz nextpnr-81c549549d88640ed77fc2b1f3da52a10b4f93ce.tar.bz2 nextpnr-81c549549d88640ed77fc2b1f3da52a10b4f93ce.zip |
ecp5: Add DCSC support
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'ecp5/arch.cc')
-rw-r--r-- | ecp5/arch.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 2c04105c..34bdfa1b 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -793,6 +793,12 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort return true; } return false; + } else if (cell->type == id_DCSC) { + if ((fromPort == id_CLK0 || fromPort == id_CLK1) && toPort == id_DCSOUT) { + delay = DelayQuad(0); + return true; + } + return false; } else if (cell->type == id_DP16KD) { return false; } else if (cell->type == id_MULT18X18D) { @@ -866,6 +872,12 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in if (port == id_CLKO) return TMG_COMB_OUTPUT; return TMG_IGNORE; + } else if (cell->type == id_DCSC) { + if (port == id_CLK0 || port == id_CLK1) + return TMG_COMB_INPUT; + if (port == id_DCSOUT) + return TMG_COMB_OUTPUT; + return TMG_IGNORE; } else if (cell->type == id_DP16KD) { if (port == id_CLKA || port == id_CLKB) return TMG_CLOCK_INPUT; |