Add remapping of DSP clk/ce/rst signals in a block.

Each DSP block contains two slices, and each slice contains multiple
MULT18X18D and ALU54B units. Each unit configures each register to use
any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are
connected per unit (so for example, two MULTs in the same block could
connect their CLK0s to different external signals). However, the
hardware only has one actual port per block, so it's required that
all CLK0 signals within a block are the same.

Because the packer is in general allowed to combine two unrelated units
into one block, it may end up combining units that use different signals
for the same port, which would eventually have caused a router failure.

This commit adds validity checks which ensure only unique signals are
used per block, and adds remapping so that conflicting signals are
automatically reassigned when possible and required.

1 files changed, 4 insertions, 0 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index eb874704..a7041e04 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -634,6 +634,10 @@ bool Arch::place()
         for (auto &cell : cells)
             cell.second->belStrength = STRENGTH_LOCKED;
 
+    // Once placement is complete, DSP slices sharing a block may need
+    // CLK/CE/RST ports remapped to avoid conflicting assignments.
+    remap_dsp_blocks();
+
     getCtx()->settings[id_place] = 1;
 
     archInfoToAttributes();