Merge pull request #44 from YosysHQ/improve_timing_spec

Speed up budget allocator using topographical ordering and update cell timing API

1 files changed, 2 insertions, 4 deletions

diff --git a/ecp5/arch.h b/ecp5/arch.h
index 55c1caa1..8a212ed0 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -828,10 +828,8 @@ struct Arch : BaseCtx
     // Get the delay through a cell from one port to another, returning false
     // if no path exists
     bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
-    // Get the associated clock to a port, or empty if the port is combinational
-    IdString getPortClock(const CellInfo *cell, IdString port) const;
-    // Return true if a port is a clock
-    bool isClockPort(const CellInfo *cell, IdString port) const;
+    // Get the port class, also setting clockPort if applicable
+    TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const;
     // Return true if a port is a net
     bool isGlobalNet(const NetInfo *net) const;