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authorDavid Shah <dave@ds0.me>2018-11-12 13:42:25 +0000
committerDavid Shah <dave@ds0.me>2018-11-12 14:03:58 +0000
commitfc5e6bec9ab8bf2c25b2b943de4013daf727dfb8 (patch)
tree1f3c4171cb20e3ec8123ceef576c383fa0034d24 /ecp5/arch_pybindings.cc
parent11579a1046640a21b79aa6a1f579d3464267d0a1 (diff)
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timing: Add support for clock constraints
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5/arch_pybindings.cc')
-rw-r--r--ecp5/arch_pybindings.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc
index 9312b4ad..5e73a673 100644
--- a/ecp5/arch_pybindings.cc
+++ b/ecp5/arch_pybindings.cc
@@ -130,6 +130,10 @@ void arch_wrap_python()
"cells");
readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
"nets");
+
+ fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
+ pass_through<float>>::def_wrap(ctx_cls, "addClock");
+
WRAP_RANGE(Bel, conv_to_str<BelId>);
WRAP_RANGE(Wire, conv_to_str<WireId>);
WRAP_RANGE(AllPip, conv_to_str<PipId>);