Alter MULT18X18D timing db based on register config

If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.

This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.

Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.

1 files changed, 7 insertions, 1 deletions

diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index 0f197345..d32e4a23 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -187,8 +187,14 @@ struct ArchCellInfo
         // Which timing information to use for a DP16KD. Depends on registering
         // configuration.
         nextpnr_ecp5::IdString regmode_timing_id;
-
     } ramInfo;
+    struct
+    {
+        bool is_in_a_registered;
+        bool is_in_b_registered;
+        bool is_output_registered;
+        nextpnr_ecp5::IdString timing_id;
+    } multInfo;
 };
 
 NEXTPNR_NAMESPACE_END