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| author | Clifford Wolf <clifford@clifford.at> | 2018-07-20 17:13:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-07-20 17:13:26 +0200 |
| commit | e16b4a325e2b0721e29cba93804923dedf74a68c (patch) | |
| tree | a80aa31ed8be848d460cd90410a91f24da14cea9 /ecp5/synth/simple_map.v | |
| parent | c0f1af87f6c1c6843e536a87ef88e39fa3428c5b (diff) | |
| parent | 6c835d76f27af79813299419780c039eb2a8b02e (diff) | |
| download | nextpnr-e16b4a325e2b0721e29cba93804923dedf74a68c.tar.gz nextpnr-e16b4a325e2b0721e29cba93804923dedf74a68c.tar.bz2 nextpnr-e16b4a325e2b0721e29cba93804923dedf74a68c.zip | |
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapi
Diffstat (limited to 'ecp5/synth/simple_map.v')
| -rw-r--r-- | ecp5/synth/simple_map.v | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/ecp5/synth/simple_map.v b/ecp5/synth/simple_map.v deleted file mode 100644 index 550fa92c..00000000 --- a/ecp5/synth/simple_map.v +++ /dev/null @@ -1,68 +0,0 @@ -module \$_DFF_P_ (input D, C, output Q); - TRELLIS_SLICE #( - .MODE("LOGIC"), - .CLKMUX("CLK"), - .CEMUX("1"), - .REG0_SD("0"), - .REG0_REGSET("RESET"), - .SRMODE("LSR_OVER_CE"), - .GSR("DISABLED") - ) _TECHMAP_REPLACE_ ( - .CLK(C), - .M0(D), - .Q0(Q) - ); -endmodule - -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - - input [WIDTH-1:0] A; - output Y; - - generate - if (WIDTH == 1) begin - TRELLIS_SLICE #( - .MODE("LOGIC"), - .LUT0_INITVAL({8{LUT[1:0]}}) - ) _TECHMAP_REPLACE_ ( - .A0(A[0]), - .F0(Y) - ); - end - if (WIDTH == 2) begin - TRELLIS_SLICE #( - .MODE("LOGIC"), - .LUT0_INITVAL({4{LUT[3:0]}}) - ) _TECHMAP_REPLACE_ ( - .A0(A[0]), - .B0(A[1]), - .F0(Y) - ); - end - if (WIDTH == 3) begin - TRELLIS_SLICE #( - .MODE("LOGIC"), - .LUT0_INITVAL({2{LUT[7:0]}}) - ) _TECHMAP_REPLACE_ ( - .A0(A[0]), - .B0(A[1]), - .C0(A[2]), - .F0(Y) - ); - end - if (WIDTH == 4) begin - TRELLIS_SLICE #( - .MODE("LOGIC"), - .LUT0_INITVAL(LUT) - ) _TECHMAP_REPLACE_ ( - .A0(A[0]), - .B0(A[1]), - .C0(A[2]), - .D0(A[3]), - .F0(Y) - ); - end - endgenerate -endmodule |