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author | gatecat <gatecat@ds0.me> | 2021-04-02 09:46:21 +0100 |
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committer | GitHub <noreply@github.com> | 2021-04-02 09:46:21 +0100 |
commit | bb6079133c9b0de9db3e39735d160c1a161ec981 (patch) | |
tree | c73ef33d274dba1c7c715b9fbe9af867feae4686 /fpga_interchange/arch.cc | |
parent | ec98fee1eefd61d17ccfaf58bae72e1cc0f9e5e3 (diff) | |
parent | 3a85088d6653b11abdf039c334814da97d0e2949 (diff) | |
download | nextpnr-bb6079133c9b0de9db3e39735d160c1a161ec981.tar.gz nextpnr-bb6079133c9b0de9db3e39735d160c1a161ec981.tar.bz2 nextpnr-bb6079133c9b0de9db3e39735d160c1a161ec981.zip |
Merge pull request #658 from litghost/increment_chipdb
[interchange] Update to v6 of FPGA interchange chipdb.
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r-- | fpga_interchange/arch.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 2e1c452a..0d6cc4de 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -247,10 +247,13 @@ Arch::Arch(ArchArgs args) : args(args) LutElement &element = elements.back(); element.width = lut_element.width; for (auto &lut_bel : lut_element.lut_bels) { - auto result = element.lut_bels.emplace(IdString(lut_bel.name), LutBel()); + IdString name(lut_bel.name); + auto result = element.lut_bels.emplace(name, LutBel()); NPNR_ASSERT(result.second); LutBel &lut = result.first->second; + lut.name = name; + lut.low_bit = lut_bel.low_bit; lut.high_bit = lut_bel.high_bit; @@ -260,6 +263,8 @@ Arch::Arch(ArchArgs args) : args(args) lut.pins.push_back(pin); lut.pin_to_index[pin] = i; } + + lut.output_pin = IdString(lut_bel.out_pin); } element.compute_pin_order(); |