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authorAlessandro Comodi <acomodi@antmicro.com>2021-06-10 13:46:53 +0200
committerAlessandro Comodi <acomodi@antmicro.com>2021-06-11 11:19:01 +0200
commit64b45848d7730077e5eddab93886c40530c4cd71 (patch)
tree9b66f5e02f67bcd4a4dfd171c55a4055ac762c79 /fpga_interchange/arch.h
parentd72c10cb6cf44467fdf6b8c6846a7b2cb925a6b0 (diff)
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interchange: run clang formatter
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/arch.h')
-rw-r--r--fpga_interchange/arch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 83471167..77a7ae59 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -853,7 +853,7 @@ struct Arch : ArchAPI<ArchRanges>
const CellInfo *cell = tile_status.boundcells[bel.index];
if (cell != nullptr) {
- if(cell->cluster == ClusterId() && !dedicated_interconnect.isBelLocationValid(bel, cell))
+ if (cell->cluster == ClusterId() && !dedicated_interconnect.isBelLocationValid(bel, cell))
return false;
if (io_port_types.count(cell->type)) {