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authorgatecat <gatecat@ds0.me>2021-02-16 09:48:40 +0000
committerGitHub <noreply@github.com>2021-02-16 09:48:40 +0000
commit815b57b9e1f0c0a7176d146a29cef763bebf343f (patch)
treeffadcd3a1026e94937f082ddf4ab59f56099ca39 /fpga_interchange/arch.h
parent9fc02041fe7bdcbac99e54f30423b2c39b92bb8a (diff)
parent1be70320b991f0f9d3f834a2aa4378a30509ef79 (diff)
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Merge pull request #583 from litghost/add_fpga_interchange_front_and_backend
Add FPGA interchange front and backend
Diffstat (limited to 'fpga_interchange/arch.h')
-rw-r--r--fpga_interchange/arch.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 886978f1..b152bd0e 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -199,6 +199,12 @@ inline const BelInfoPOD &bel_info(const ChipInfoPOD *chip_info, BelId bel)
return loc_info(chip_info, bel).bel_data[bel.index];
}
+inline const PipInfoPOD &pip_info(const ChipInfoPOD *chip_info, PipId pip)
+{
+ NPNR_ASSERT(pip != PipId());
+ return loc_info(chip_info, pip).pip_data[pip.index];
+}
+
struct BelIterator
{
const ChipInfoPOD *chip;
@@ -742,6 +748,8 @@ struct Arch : ArchAPI<ArchRanges>
}
char getNameDelimiter() const override { return '/'; }
+ std::string get_part() const;
+
// -------------------------------------------------
void setup_byname() const;
@@ -1308,6 +1316,8 @@ struct Arch : ArchAPI<ArchRanges>
void read_logical_netlist(const std::string &filename);
void write_physical_netlist(const std::string &filename) const;
void parse_xdc(const std::string &filename);
+
+ std::unordered_set<IdString> io_port_types;
};
NEXTPNR_NAMESPACE_END