aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/arch.h
diff options
context:
space:
mode:
authorgatecat <gatecat@ds0.me>2021-07-10 23:24:38 +0100
committergatecat <gatecat@ds0.me>2021-07-10 23:24:38 +0100
commit8531658019a5d8f7834c6054e10c8438d8006505 (patch)
tree9ed98754646aeea1c7c2cae749c7f3f20f57fc40 /fpga_interchange/arch.h
parentd290766101a62d575c3e6aacbecde46ecab349f6 (diff)
parent478456e6e98c05ee5f810de0c0206daee25482f3 (diff)
downloadnextpnr-8531658019a5d8f7834c6054e10c8438d8006505.tar.gz
nextpnr-8531658019a5d8f7834c6054e10c8438d8006505.tar.bz2
nextpnr-8531658019a5d8f7834c6054e10c8438d8006505.zip
Merge branch 'master' of github.com:YosysHQ/nextpnr
Diffstat (limited to 'fpga_interchange/arch.h')
-rw-r--r--fpga_interchange/arch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 896a603a..630c4480 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -855,7 +855,7 @@ struct Arch : ArchAPI<ArchRanges>
const CellInfo *cell = tile_status.boundcells[bel.index];
if (cell != nullptr) {
- if (cell->cluster == ClusterId() && !dedicated_interconnect.isBelLocationValid(bel, cell))
+ if (!dedicated_interconnect.isBelLocationValid(bel, cell))
return false;
if (io_port_types.count(cell->type)) {