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| author | gatecat <gatecat@ds0.me> | 2021-04-25 16:29:13 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-21 10:00:35 +0100 |
| commit | 64f5b1d031960b779ca788d5fc92843c2213a045 (patch) | |
| tree | 481120d3b3ba5b09ecd7cb577ca7d52f41703c75 /fpga_interchange/arch_pybindings.cc | |
| parent | a146dbdb03413ca32ca96c98ae5f3bdaf73d9126 (diff) | |
| download | nextpnr-64f5b1d031960b779ca788d5fc92843c2213a045.tar.gz nextpnr-64f5b1d031960b779ca788d5fc92843c2213a045.tar.bz2 nextpnr-64f5b1d031960b779ca788d5fc92843c2213a045.zip | |
interchange: Don't error out on missing cell ports
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch_pybindings.cc')
0 files changed, 0 insertions, 0 deletions