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authorgatecat <gatecat@ds0.me>2021-04-25 16:29:13 +0100
committergatecat <gatecat@ds0.me>2021-05-21 10:00:35 +0100
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interchange: Don't error out on missing cell ports
This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
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