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authorgatecat <gatecat@ds0.me>2021-03-29 18:23:16 +0100
committerGitHub <noreply@github.com>2021-03-29 18:23:16 +0100
commit692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3 (patch)
treeebe474f5cacc1206b083c7a09e77d431b4a61e61 /fpga_interchange/archdefs.h
parent4419c36db5556d2a7f600517d6a4b5673067579d (diff)
parentf33d02dca9f6080c2497a4e058554c9908677888 (diff)
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Merge pull request #645 from litghost/add_counter_and_ram
FPGA interchange: Add counter and ram tests
Diffstat (limited to 'fpga_interchange/archdefs.h')
-rw-r--r--fpga_interchange/archdefs.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h
index 8364520d..23bff4f3 100644
--- a/fpga_interchange/archdefs.h
+++ b/fpga_interchange/archdefs.h
@@ -109,10 +109,9 @@ struct ArchNetInfo
struct ArchCellInfo
{
- ArchCellInfo() : cell_mapping(-1) {}
-
- int32_t cell_mapping;
+ int32_t cell_mapping = -1;
HashTables::HashMap<IdString, std::vector<IdString>> cell_bel_pins;
+ HashTables::HashMap<IdString, std::vector<IdString>> masked_cell_bel_pins;
HashTables::HashSet<IdString> const_ports;
LutCell lut_cell;
};