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| author | gatecat <gatecat@ds0.me> | 2021-06-11 11:36:42 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-11 11:36:42 +0100 |
| commit | 1c7efdc02ce3e36558374e641ea07833cb3a1849 (patch) | |
| tree | b68e79f3e3972e913a0fba94ea7b654208199426 /fpga_interchange/chipdb.h | |
| parent | 7278d3c0edbc6f92ef4c69d7c5db66e811c7e9c4 (diff) | |
| parent | aa1784c5d9d0b5a3c26b0a148afa6b2de3dc68de (diff) | |
| download | nextpnr-1c7efdc02ce3e36558374e641ea07833cb3a1849.tar.gz nextpnr-1c7efdc02ce3e36558374e641ea07833cb3a1849.tar.bz2 nextpnr-1c7efdc02ce3e36558374e641ea07833cb3a1849.zip | |
Merge pull request #720 from acomodi/interchange-clusters
interchange: enable clusters support
Diffstat (limited to 'fpga_interchange/chipdb.h')
| -rw-r--r-- | fpga_interchange/chipdb.h | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index 155c2bb2..fde35e7f 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 10; +static constexpr int32_t kExpectedChipInfoVersion = 11; // Flattened site indexing. // @@ -402,6 +402,27 @@ NPNR_PACKED_STRUCT(struct MacroExpansionPOD { RelSlice<MacroParamMapRulePOD> param_rules; }); +NPNR_PACKED_STRUCT(struct ClusterCellPortPOD { + uint32_t cell; + uint32_t port; +}); + +NPNR_PACKED_STRUCT(struct ChainablePortPOD { + uint32_t cell_source; + uint32_t cell_sink; + uint32_t bel_source; + uint32_t bel_sink; + int16_t avg_x_offset; + int16_t avg_y_offset; +}); + +NPNR_PACKED_STRUCT(struct ClusterPOD { + uint32_t name; + RelSlice<uint32_t> root_cell_types; + RelSlice<ChainablePortPOD> chainable_ports; + RelSlice<ClusterCellPortPOD> cluster_cells_map; +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr<char> name; RelPtr<char> generator; @@ -421,6 +442,8 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelSlice<MacroPOD> macros; RelSlice<MacroExpansionPOD> macro_rules; + RelSlice<ClusterPOD> clusters; + // BEL bucket constids. RelSlice<int32_t> bel_buckets; @@ -460,6 +483,11 @@ inline const SiteInstInfoPOD &site_inst_info(const ChipInfoPOD *chip_info, int32 return chip_info->sites[chip_info->tiles[tile].sites[site]]; } +inline const ClusterPOD &cluster_info(const ChipInfoPOD *chip_info, int32_t cluster) +{ + return chip_info->clusters[cluster]; +} + enum SyntheticType { NOT_SYNTH = 0, |