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| author | gatecat <gatecat@ds0.me> | 2021-06-30 13:00:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-30 13:00:12 +0100 |
| commit | 152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e (patch) | |
| tree | 8bf5a86b5b473e535686ac836e53c44eff3ccdab /fpga_interchange/dedicated_interconnect.cc | |
| parent | 91b998bb11e4bce04ecd6e2a81119714fb4640ae (diff) | |
| parent | b3882f8324507ed503ff481abda3dffded0d0b67 (diff) | |
| download | nextpnr-152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e.tar.gz nextpnr-152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e.tar.bz2 nextpnr-152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e.zip | |
Merge pull request #739 from YosysHQ/gatecat/usp-io-macro
interchange: Place entire IO macro based on routeability
Diffstat (limited to 'fpga_interchange/dedicated_interconnect.cc')
| -rw-r--r-- | fpga_interchange/dedicated_interconnect.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc index d78743ac..6a2d16bb 100644 --- a/fpga_interchange/dedicated_interconnect.cc +++ b/fpga_interchange/dedicated_interconnect.cc @@ -87,7 +87,10 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B WireNode wire_node; wire_node.wire = src_wire; - wire_node.state = IN_SOURCE_SITE; + if (src_wire.tile == dst_wire.tile && src_wire_data.site == dst_wire_data.site) + wire_node.state = IN_SINK_SITE; + else + wire_node.state = IN_SOURCE_SITE; wire_node.depth = 0; nodes_to_expand.push_back(wire_node); |