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author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-03-25 17:11:06 -0700 |
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committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-03-25 17:56:11 -0700 |
commit | c8dccd3e7bec95c635ebe435c8454ffe10edd6f3 (patch) | |
tree | 3d73b20a24fab6cc57194247c2b1a31ea1fc4028 /fpga_interchange/dedicated_interconnect.cc | |
parent | cc4f2b451613f2d7152e1d42d2e4d0d59887df1c (diff) | |
download | nextpnr-c8dccd3e7bec95c635ebe435c8454ffe10edd6f3.tar.gz nextpnr-c8dccd3e7bec95c635ebe435c8454ffe10edd6f3.tar.bz2 nextpnr-c8dccd3e7bec95c635ebe435c8454ffe10edd6f3.zip |
Implement debugging tools for site router.
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/dedicated_interconnect.cc')
-rw-r--r-- | fpga_interchange/dedicated_interconnect.cc | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc index 988b13ab..1038ed1f 100644 --- a/fpga_interchange/dedicated_interconnect.cc +++ b/fpga_interchange/dedicated_interconnect.cc @@ -365,6 +365,35 @@ bool DedicatedInterconnect::isBelLocationValid(BelId bel, const CellInfo *cell) return true; } +void DedicatedInterconnect::explain_bel_status(BelId bel, const CellInfo *cell) const +{ + NPNR_ASSERT(bel != BelId()); + + for (const auto &port_pair : cell->ports) { + IdString port_name = port_pair.first; + NetInfo *net = port_pair.second.net; + if (net == nullptr) { + continue; + } + + // This net doesn't have a driver, probably not valid? + NPNR_ASSERT(net->driver.cell != nullptr); + + // Only check sink BELs. + if (net->driver.cell == cell && net->driver.port == port_name) { + if (!is_driver_on_net_valid(bel, cell, port_name, net)) { + log_info("Driver %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx), + net->name.c_str(ctx)); + } + } else { + if (!is_sink_on_net_valid(bel, cell, port_name, net)) { + log_info("Sink %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx), + net->name.c_str(ctx)); + } + } + } +} + void DedicatedInterconnect::print_dedicated_interconnect() const { log_info("Found %zu sinks with dedicated interconnect\n", sinks.size()); |