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authorgatecat <gatecat@ds0.me>2021-03-29 18:23:16 +0100
committerGitHub <noreply@github.com>2021-03-29 18:23:16 +0100
commit692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3 (patch)
treeebe474f5cacc1206b083c7a09e77d431b4a61e61 /fpga_interchange/dedicated_interconnect.h
parent4419c36db5556d2a7f600517d6a4b5673067579d (diff)
parentf33d02dca9f6080c2497a4e058554c9908677888 (diff)
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Merge pull request #645 from litghost/add_counter_and_ram
FPGA interchange: Add counter and ram tests
Diffstat (limited to 'fpga_interchange/dedicated_interconnect.h')
-rw-r--r--fpga_interchange/dedicated_interconnect.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga_interchange/dedicated_interconnect.h b/fpga_interchange/dedicated_interconnect.h
index 41adea15..900a82f3 100644
--- a/fpga_interchange/dedicated_interconnect.h
+++ b/fpga_interchange/dedicated_interconnect.h
@@ -133,6 +133,7 @@ struct DedicatedInterconnect
//
// Note: Only BEL pin sinks are checked.
bool isBelLocationValid(BelId bel, const CellInfo *cell) const;
+ void explain_bel_status(BelId bel, const CellInfo *cell) const;
void find_dedicated_interconnect();
void print_dedicated_interconnect() const;