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| author | Alessandro Comodi <acomodi@antmicro.com> | 2021-03-12 13:53:09 +0100 |
|---|---|---|
| committer | Alessandro Comodi <acomodi@antmicro.com> | 2021-03-16 15:39:01 +0100 |
| commit | 77ffdd7fd4e90e0da43e81b1f5e021b08ee64a9f (patch) | |
| tree | 143ce61b476d33d2b0ddd63d5beb872f5d077949 /fpga_interchange/examples/const_wire | |
| parent | 6a08b0d733e928e5e7c180dee21829f7db2d9ccf (diff) | |
| download | nextpnr-77ffdd7fd4e90e0da43e81b1f5e021b08ee64a9f.tar.gz nextpnr-77ffdd7fd4e90e0da43e81b1f5e021b08ee64a9f.tar.bz2 nextpnr-77ffdd7fd4e90e0da43e81b1f5e021b08ee64a9f.zip | |
fpga_interchange: tests: add cmake functions
Also move all tests in a tests directory
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/examples/const_wire')
| -rw-r--r-- | fpga_interchange/examples/const_wire/Makefile | 8 | ||||
| -rw-r--r-- | fpga_interchange/examples/const_wire/run.tcl | 14 | ||||
| -rw-r--r-- | fpga_interchange/examples/const_wire/wire.v | 8 | ||||
| -rw-r--r-- | fpga_interchange/examples/const_wire/wire.xdc | 9 |
4 files changed, 0 insertions, 39 deletions
diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile deleted file mode 100644 index 49194f53..00000000 --- a/fpga_interchange/examples/const_wire/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -DESIGN := wire -DESIGN_TOP := top -PACKAGE := csg324 - -include ../template.mk - -build/wire.json: wire.v | build - yosys -c run.tcl diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl deleted file mode 100644 index 9127be20..00000000 --- a/fpga_interchange/examples/const_wire/run.tcl +++ /dev/null @@ -1,14 +0,0 @@ -yosys -import - -read_verilog wire.v - -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp - -# opt_expr -undriven makes sure all nets are driven, if only by the $undef -# net. -opt_expr -undriven -opt_clean - -setundef -zero -params - -write_json build/wire.json diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v deleted file mode 100644 index 5b1ab692..00000000 --- a/fpga_interchange/examples/const_wire/wire.v +++ /dev/null @@ -1,8 +0,0 @@ -module top(output o, output o2, output o3, output o4); - -assign o = 1'b0; -assign o2 = 1'b1; -assign o3 = 1'b0; -assign o4 = 1'b1; - -endmodule diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc deleted file mode 100644 index 0d96fc45..00000000 --- a/fpga_interchange/examples/const_wire/wire.xdc +++ /dev/null @@ -1,9 +0,0 @@ -set_property PACKAGE_PIN N15 [get_ports o] -set_property PACKAGE_PIN N16 [get_ports o2] -set_property PACKAGE_PIN P17 [get_ports o3] -set_property PACKAGE_PIN R17 [get_ports o4] - -set_property IOSTANDARD LVCMOS33 [get_ports o] -set_property IOSTANDARD LVCMOS33 [get_ports o2] -set_property IOSTANDARD LVCMOS33 [get_ports o3] -set_property IOSTANDARD LVCMOS33 [get_ports o4] |