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| author | gatecat <gatecat@ds0.me> | 2021-03-25 16:03:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-25 16:03:22 +0000 |
| commit | f233bee9701ea191862d26616d68dab08ba7d2b0 (patch) | |
| tree | a23f37b687bffa78976d39df4c212407e539732c /fpga_interchange/examples/devices | |
| parent | 3cc50a5744beeae63ffb9ecd2064666e90d26be4 (diff) | |
| parent | c4cb86efe9dece4a837bdd490f5d7f78d2b4480f (diff) | |
| download | nextpnr-f233bee9701ea191862d26616d68dab08ba7d2b0.tar.gz nextpnr-f233bee9701ea191862d26616d68dab08ba7d2b0.tar.bz2 nextpnr-f233bee9701ea191862d26616d68dab08ba7d2b0.zip | |
Merge pull request #628 from acomodi/add-interchange-devices
fpga_interchange: add more devices
Diffstat (limited to 'fpga_interchange/examples/devices')
7 files changed, 156 insertions, 0 deletions
diff --git a/fpga_interchange/examples/devices/CMakeLists.txt b/fpga_interchange/examples/devices/CMakeLists.txt index 5b96ac80..965e4aa8 100644 --- a/fpga_interchange/examples/devices/CMakeLists.txt +++ b/fpga_interchange/examples/devices/CMakeLists.txt @@ -1 +1,7 @@ +# Artix-7 devices add_subdirectory(xc7a35t) +add_subdirectory(xc7a100t) +add_subdirectory(xc7a200t) + +# Zynq-7 devices +add_subdirectory(xc7z010) diff --git a/fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt new file mode 100644 index 00000000..955ee8ca --- /dev/null +++ b/fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt @@ -0,0 +1,14 @@ +generate_xc7_device_db( + device xc7a100t + part xc7a100tcsg324-1 + device_target xc7a100t_target +) + +generate_chipdb( + family ${family} + device xc7a100t + part xc7a100tcsg324-1 + device_target ${xc7a100t_target} + device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml + test_package csg324 +) diff --git a/fpga_interchange/examples/devices/xc7a100t/test_data.yaml b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml new file mode 100644 index 00000000..268d180a --- /dev/null +++ b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml @@ -0,0 +1,36 @@ +pip_test: + - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 + dst_wire: SLICE_X15Y93.SLICEL/D3 +pip_chain_test: + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE + - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0 + - INT_R_X3Y145/GND_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE + - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1 + - INT_R_X3Y145/VCC_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE + - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1 + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE + - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0 +bel_pin_test: + - bel: SLICE_X15Y93.SLICEL/D6LUT + pin: A3 + wire: SLICE_X15Y93.SLICEL/D3 + - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND + pin: G + wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC + pin: P + wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE diff --git a/fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt new file mode 100644 index 00000000..b77d77bb --- /dev/null +++ b/fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt @@ -0,0 +1,14 @@ +generate_xc7_device_db( + device xc7a200t + part xc7a200tsbg484-1 + device_target xc7a200t_target +) + +generate_chipdb( + family ${family} + device xc7a200t + part xc7a200tsbg484-1 + device_target ${xc7a200t_target} + device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml + test_package sbg484 +) diff --git a/fpga_interchange/examples/devices/xc7a200t/test_data.yaml b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml new file mode 100644 index 00000000..268d180a --- /dev/null +++ b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml @@ -0,0 +1,36 @@ +pip_test: + - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 + dst_wire: SLICE_X15Y93.SLICEL/D3 +pip_chain_test: + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE + - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0 + - INT_R_X3Y145/GND_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE + - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1 + - INT_R_X3Y145/VCC_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE + - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1 + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE + - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0 +bel_pin_test: + - bel: SLICE_X15Y93.SLICEL/D6LUT + pin: A3 + wire: SLICE_X15Y93.SLICEL/D3 + - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND + pin: G + wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC + pin: P + wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE diff --git a/fpga_interchange/examples/devices/xc7z010/CMakeLists.txt b/fpga_interchange/examples/devices/xc7z010/CMakeLists.txt new file mode 100644 index 00000000..ec6a7728 --- /dev/null +++ b/fpga_interchange/examples/devices/xc7z010/CMakeLists.txt @@ -0,0 +1,14 @@ +generate_xc7_device_db( + device xc7z010 + part xc7z010clg400-1 + device_target xc7z010_target +) + +generate_chipdb( + family ${family} + device xc7z010 + part xc7z010clg400-1 + device_target ${xc7z010_target} + device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml + test_package clg400 +) diff --git a/fpga_interchange/examples/devices/xc7z010/test_data.yaml b/fpga_interchange/examples/devices/xc7z010/test_data.yaml new file mode 100644 index 00000000..dbc95845 --- /dev/null +++ b/fpga_interchange/examples/devices/xc7z010/test_data.yaml @@ -0,0 +1,36 @@ +pip_test: + - src_wire: CLBLM_L_X8Y69/CLBLM_L_D3 + dst_wire: SLICE_X11Y69.SLICEL/D3 +pip_chain_test: + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE + - TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0 + - INT_L_X8Y69/GND_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - TIEOFF_X9Y69.TIEOFF/$VCC_SITE_WIRE + - TIEOFF_X9Y69.TIEOFF/HARD1VCC_HARD1 + - INT_L_X8Y69/VCC_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - SLICE_X11Y69.SLICEL/$VCC_SITE_WIRE + - SLICE_X11Y69.SLICEL/CEUSEDVCC_HARD1 + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - SLICE_X11Y69.SLICEL/$GND_SITE_WIRE + - SLICE_X11Y69.SLICEL/SRUSEDGND_HARD0 +bel_pin_test: + - bel: SLICE_X14Y63.SLICEL/D6LUT + pin: A3 + wire: SLICE_X14Y63.SLICEL/D3 + - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND + pin: G + wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC + pin: P + wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE |