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authorgatecat <gatecat@ds0.me>2021-02-25 10:22:45 +0000
committerGitHub <noreply@github.com>2021-02-25 10:22:45 +0000
commitab8dfcfba4544c6733d074b24b0529d431b66d29 (patch)
treeaf212992fee7cd0a8fb27d19d0137587402fdc1b /fpga_interchange/examples/ff/ff.v
parente2cdaa653c805f9bfb6f0ab36295858e5dd3179d (diff)
parenta30043c8da1b1cc46a2dcfb90aa3a06d4f4ed4e9 (diff)
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Merge pull request #591 from litghost/add_constant_network
Add constant network support to FPGA interchange arch
Diffstat (limited to 'fpga_interchange/examples/ff/ff.v')
-rw-r--r--fpga_interchange/examples/ff/ff.v11
1 files changed, 11 insertions, 0 deletions
diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v
new file mode 100644
index 00000000..1c271042
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.v
@@ -0,0 +1,11 @@
+module top(input clk, input d, input r, output reg q);
+
+always @(posedge clk)
+begin
+ if(r)
+ q <= 1'b0;
+ else
+ q <= d;
+end
+
+endmodule