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author | gatecat <gatecat@ds0.me> | 2021-02-25 10:22:45 +0000 |
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committer | GitHub <noreply@github.com> | 2021-02-25 10:22:45 +0000 |
commit | ab8dfcfba4544c6733d074b24b0529d431b66d29 (patch) | |
tree | af212992fee7cd0a8fb27d19d0137587402fdc1b /fpga_interchange/examples/ff/ff.v | |
parent | e2cdaa653c805f9bfb6f0ab36295858e5dd3179d (diff) | |
parent | a30043c8da1b1cc46a2dcfb90aa3a06d4f4ed4e9 (diff) | |
download | nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.tar.gz nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.tar.bz2 nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.zip |
Merge pull request #591 from litghost/add_constant_network
Add constant network support to FPGA interchange arch
Diffstat (limited to 'fpga_interchange/examples/ff/ff.v')
-rw-r--r-- | fpga_interchange/examples/ff/ff.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v new file mode 100644 index 00000000..1c271042 --- /dev/null +++ b/fpga_interchange/examples/ff/ff.v @@ -0,0 +1,11 @@ +module top(input clk, input d, input r, output reg q); + +always @(posedge clk) +begin + if(r) + q <= 1'b0; + else + q <= d; +end + +endmodule |