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authorgatecat <gatecat@ds0.me>2021-03-17 14:05:49 +0000
committerGitHub <noreply@github.com>2021-03-17 14:05:49 +0000
commit5feea4497f416eafdf54f34c2b9c67ddcef3f26f (patch)
treee92427a879159b38441e6b3fc4f0e45ebc75e579 /fpga_interchange/examples/tests/const_wire/wire.v
parent701587241fb8d4b490c4998ab3f2590bc09d7f55 (diff)
parent01a95faf211d5947415ed6a9ea2b1fbedf1074cd (diff)
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Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange
Add CMake infrastructure for fpga interchange
Diffstat (limited to 'fpga_interchange/examples/tests/const_wire/wire.v')
-rw-r--r--fpga_interchange/examples/tests/const_wire/wire.v8
1 files changed, 8 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/const_wire/wire.v b/fpga_interchange/examples/tests/const_wire/wire.v
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+++ b/fpga_interchange/examples/tests/const_wire/wire.v
@@ -0,0 +1,8 @@
+module top(output o, output o2, output o3, output o4);
+
+assign o = 1'b0;
+assign o2 = 1'b1;
+assign o3 = 1'b0;
+assign o4 = 1'b1;
+
+endmodule