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authorgatecat <gatecat@ds0.me>2021-03-17 14:05:49 +0000
committerGitHub <noreply@github.com>2021-03-17 14:05:49 +0000
commit5feea4497f416eafdf54f34c2b9c67ddcef3f26f (patch)
treee92427a879159b38441e6b3fc4f0e45ebc75e579 /fpga_interchange/examples/tests/const_wire/wire_basys3.xdc
parent701587241fb8d4b490c4998ab3f2590bc09d7f55 (diff)
parent01a95faf211d5947415ed6a9ea2b1fbedf1074cd (diff)
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Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange
Add CMake infrastructure for fpga interchange
Diffstat (limited to 'fpga_interchange/examples/tests/const_wire/wire_basys3.xdc')
-rw-r--r--fpga_interchange/examples/tests/const_wire/wire_basys3.xdc9
1 files changed, 9 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/const_wire/wire_basys3.xdc b/fpga_interchange/examples/tests/const_wire/wire_basys3.xdc
new file mode 100644
index 00000000..f8435580
--- /dev/null
+++ b/fpga_interchange/examples/tests/const_wire/wire_basys3.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN U16 [get_ports o]
+set_property PACKAGE_PIN E19 [get_ports o2]
+set_property PACKAGE_PIN U19 [get_ports o3]
+set_property PACKAGE_PIN V19 [get_ports o4]
+
+set_property IOSTANDARD LVCMOS33 [get_ports o]
+set_property IOSTANDARD LVCMOS33 [get_ports o2]
+set_property IOSTANDARD LVCMOS33 [get_ports o3]
+set_property IOSTANDARD LVCMOS33 [get_ports o4]