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| author | Alessandro Comodi <acomodi@antmicro.com> | 2021-03-15 11:02:56 +0100 |
|---|---|---|
| committer | Alessandro Comodi <acomodi@antmicro.com> | 2021-03-16 15:39:02 +0100 |
| commit | f52b5b39edf3075fbee7244aabea1a12f6cdc70b (patch) | |
| tree | c576409140584d1d32e35ae3321be26cbb9a382f /fpga_interchange/examples/tests/counter/run.tcl | |
| parent | 3f3cabea2d16cd93c8d9114939b8a4fc883f09f1 (diff) | |
| download | nextpnr-f52b5b39edf3075fbee7244aabea1a12f6cdc70b.tar.gz nextpnr-f52b5b39edf3075fbee7244aabea1a12f6cdc70b.tar.bz2 nextpnr-f52b5b39edf3075fbee7244aabea1a12f6cdc70b.zip | |
fpga_interchange: tests: add techmap optional source file
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/examples/tests/counter/run.tcl')
| -rw-r--r-- | fpga_interchange/examples/tests/counter/run.tcl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl index 7cd9f10f..ffea3b2e 100644 --- a/fpga_interchange/examples/tests/counter/run.tcl +++ b/fpga_interchange/examples/tests/counter/run.tcl @@ -3,7 +3,7 @@ yosys -import read_verilog $::env(SOURCES) synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp -techmap -map ../remap.v +techmap -map $::env(TECHMAP) # opt_expr -undriven makes sure all nets are driven, if only by the $undef # net. |