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| author | Alessandro Comodi <acomodi@antmicro.com> | 2021-06-02 09:49:30 +0200 |
|---|---|---|
| committer | Alessandro Comodi <acomodi@antmicro.com> | 2021-06-11 11:19:01 +0200 |
| commit | 104536b7aae5970ae1d1e95394f26fbf04603d12 (patch) | |
| tree | 0f1fad9a952f272e6436456077fe54ba3a7730ea /fpga_interchange/examples/tests/counter/run_xilinx.tcl | |
| parent | 7278d3c0edbc6f92ef4c69d7c5db66e811c7e9c4 (diff) | |
| download | nextpnr-104536b7aae5970ae1d1e95394f26fbf04603d12.tar.gz nextpnr-104536b7aae5970ae1d1e95394f26fbf04603d12.tar.bz2 nextpnr-104536b7aae5970ae1d1e95394f26fbf04603d12.zip | |
interchange: add support for generating BEL clusters
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/examples/tests/counter/run_xilinx.tcl')
0 files changed, 0 insertions, 0 deletions